Non-punch-through reverse-conducting power semiconductor device and method for producing same

Abstract

A thin non-punch-through semiconductor device with a patterned collector layer on the collector side is proposed. The thin NPT RC-IGBT semiconductor device has a collector layer with a pattern of p/n shorts, an emitter side structured as a functional MOS cell, a base layer arranged between the emitter and the collector sides, but without the use of a buffer/field-stop layer. A low doped bipolar gain control layer having a thickness of less than 10 μm may be used in combination with a short pattern of the collector to reduce the bipolar gain and achieve thinner devices with lower losses and high operating temperature capability. The doping concentration of the base layer and a thickness of the base layer are adapted such that the distance from the end of the electric field region to the patterned collector, at breakdown voltage, is less than 15% of the total device thickness.

Claims

1. A non-punch-through reverse conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor with layers of a first and a second conductivity type, a first main side, and a second main side, wherein the first main side is arranged opposite of the second main side, having at least a four-layer structure comprising: an emitter electrode on the first main side, which lies opposite a collector electrode on the second main side, wherein the first main side is structured as a functional MOSFET type cell that has planar gate electrodes or trench-based gate electrodes, a base layer arranged between the first main side and the second main side, and a patterned collector layer on the second main side with alternating first and second conductivity type regions that form collector shorts, a bipolar gain control layer arranged between the base layer and the patterned collector layer, wherein the bipolar gain control layer has a same first conductivity type as the base layer and has a peak doping concentration below 1×10.sup.16 cm.sup.−3, and a thickness between 1 μm and 10 μm; wherein, up to an avalanche breakdown voltage V.sub.bd of the semiconductor device: the bipolar gain control layer is arranged entirely in a space charge free zone; and a thickness and a doping concentration of the base layer are adapted such that a thickness of the space charge free zone on the second main side is less than 15% of a total device thickness at the avalanche breakdown voltage V.sub.bd ; wherein a thickness of the space charge free zone (W.sub.SCF) is given by $W_{SCF}\left(\mathrm{\mu m}\right)=\left(0.125\mathrm{to}0.133\right)\left(\frac{\mathrm{\mu m}}{V}\right)\times V_{\mathrm{rati}ng}\left(V\right)-0.1\left(\frac{\mathrm{\mu m}}{V}\right)\times V_{bd}\left(V\right)$ where V.sub.rating is a voltage rating of the non-punch-through reverse conducting semiconductor device and is one of 600 V, 900 V, 1200 V, or 1700 V.

2. The non-punch-through reverse conducting semiconductor device of claim 1, wherein the avalanche breakdown voltage V.sub.bd is defined as $V_{\mathrm{bd}}\left(V\right)=\frac{{\mathrm{.Math.}}_s{E}_c^2}{2q{N}_{DB}}=\frac{1.31\times 10^{17}\left(\frac{V}{{\mathrm{cm}}^3}\right)}{N_{DB}\left(\frac{1}{{\mathrm{cm}}^3}\right)}$ where ε.sub.s is a permittivity of silicon=1.05×10.sup.−12 F/cm, q is an electron charge=1.602×10.sup.−19 C , E.sub.c is the critical electric field and assumed to be 2×10.sup.5 V/cm and N.sub.DB is the doping concentration of the base region.

3. The non-punch-through reverse conducting semiconductor device of claim 1, wherein a gain of the insulated gate bipolar transistor (b.sub.PNP) is defined as ${\beta }_{PNP}=\frac{n_{iSCF}^2}{n_{iC}^2}.Math.\frac{D_{pSCF}}{D_{nC}}.Math.\frac{L_{nC}}{W_{SCF}}.Math.\frac{N_{AC}}{N_{DSCF}}$ where W.sub.SCF is the thickness of the space charge free zone, N.sub.DSCF and D.sub.pSCF represent a background doping concentration and a minority carrier diffusion coefficient in the space charge free (SCF) zone, N.sub.AC, D.sub.nC and L.sub.nC represent a background doping concentration, a minority carrier diffusion coefficient and a diffusion length of electrons respectively in the collector's second conductive type region.

4. The non-punch-through reverse conducting semiconductor device of claim 1, wherein a peak doping concentration of the bipolar gain control layer is less than 1×10.sup.15 cm.sup.−3 and a thickness of the bipolar gain control layer is between 1 μm and 3 μm.

5. The non-punch-through reverse conducting semiconductor device of claim 1, wherein a doping concentration of the base layer and the thickness of the base layer are adapted such that the avalanche break down voltage of the semiconductor device is below 2500 V.

6. The non-punch-through reverse conducting semiconductor device of claim 1, wherein the semiconductor device has a voltage rating value less than 1800 V.

7. The non-punch-through reverse conducting semiconductor device of claim 1, wherein a width of the second conductivity regions of the patterned collector layer is greater than 50 um.

8. The non-punch-through reverse conducting semiconductor device of claim 7, wherein a width of the first conductivity regions of the patterned collector layer is greater than 10 um.

9. The non-punch-through reverse conducting semiconductor device of claim 8, wherein within the patterned collector layer, the width of the second conductivity regions is greater than or equal to the width of the first conductivity regions.

10. A system comprising one or more non-punch-through reverse conducting semiconductor devices of claim 1.

11. The system of claim 10 wherein the one or more non-punch-through reverse conducting semiconductor devices are thin non-punch-through reverse conducting Insulated Gate Bipolar Transistors.

Description

BRIEF DESCRIPTION

(1) The embodiments of the invention will be explained in more detail in the following text with reference to the attached exemplary drawings, in which:

(2) FIG. 1 shows the cross sections of prior art NPT-IGBT and PT-IGBT, while depicting the potential thickness reduction achieved with PT-IGBT compared to a NPT-IGBT.

(3) FIG. 2 shows a representation of the corresponding doping concentration profile and electrical field at V.sub.bd of prior art NPT-IGBT and PT-IGBT, while depicting the potential thickness reduction achieved with PT-IGBT compared to a NPT-IGBT.

(4) FIG. 3 shows the cross sections of prior art NPT CS-IGBT or NPT RC-IGBT and PT CS-IGBT or PT CS-IGBT, while depicting the potential thickness reduction achieved with PT device compared to a NPT device.

(5) FIG. 4 shows a representation of the corresponding doping concentration profile and electrical field at V.sub.bd of prior art NPT CS-IGBT or NPT RC-IGBT and PT CS-IGBT or PT CS-IGBT, while depicting the potential thickness reduction achieved with the PT device compared to a NPT device.

(6) FIG. 5 shows the cross sections of both prior art NPT RC-IGBT and Thin NPT RC-IGBT according to an embodiment of the invention, while depicting the potential thickness reduction achieved with the new thin NPT RC-IGBT compared to a prior art NPT RC-IGBT.

(7) FIG. 6 show a representation of the corresponding doping concentration profile and electrical field at V.sub.bd of a prior art NPT RC-IGBT and a Thin NPT RC-IGBT according to an embodiment of the invention, while depicting the potential thickness reduction achieved with the new thin NPT RC-IGBT compared to a prior art NPT RC-IGBT.

(8) FIG. 7 shows a plan view of the structures of first and second regions of a reverse-conducting IGBT according to the invention;

(9) FIG. 8: shows a plan view of the structures of first and second regions on the collector side of another reverse-conducting IGBT according to the invention;

(10) FIG. 9: shows a plan view of the structures of first and second regions on the collector side of another reverse-conducting IGBT according to the invention;

(11) FIG. 10: shows a graph representing the blocking characteristics for the collector leakage current versus the collector emitter voltage at 125° C. of the non-punch-through NPT IGBT and NPT RC-IGBT, and punch-through PT-IGBT in comparison to the thin non-punch-through NPT RC-IGBT according to embodiments of the invention.

(12) FIG. 11: shows a graph representing the blocking characteristics for the collector leakage current versus the collector emitter voltage at 200° C. of the thin non-punch-through NPT RC-IGBT according to embodiments of the invention with different BGC layer peak doping concentrations, in comparison to a conventional/prior art PT-IGBT.

(13) FIGS. 12-14: show the different manufacturing steps of a thin NPT reverse-conducting IGBT according to the invention.

(14) FIG. 15: shows the cross section of another inventive reverse-conducting IGBT with an enhancement layer according to the invention.

(15) FIG. 16: shows the cross section of another inventive reverse-conducting IGBT with trench gate electrodes according to the invention.

DETAILED DESCRIPTION

(16) It may be an object of the present invention to provide a thin non-punch-through reverse conducting Insulated gate bipolar transistor NPT RC-IGBT with improved electrical characteristics. Furthermore, it may be an object of the present invention to provide a method for producing such non-punch-through reverse conducting semiconductor device.

(17) These objects may be met by the subject matter of the independent claims. Embodiments of the invention are described with respect to the dependent claims.

(18) Aspects of the present invention have been developed based on the following findings: in conventional NPT semiconductor devices such as for example NPT insulated gate bipolar transistors NPT-IGBT, a safe distance “space charge free zone (scfz)” of more than 15% of the total device thickness is conventionally implemented to support the separation of the end electric field (or space charge) region and collector side up to the break down voltage V.sub.bd. For example, the breakdown voltage V.sub.bd of an NPT-IGBT with a voltage rating V.sub.rating of 1200 V having a thickness of 180 μm may be 1300 V. The implemented safe distance is adjusted to be more than 30 μm in this case by controlling the n-type base resistivity to have a value around 50 ohm.Math.cm, which corresponds to a doping concentration of 8.6e13/cm.sup.3. Conventionally, a thickness below 170 μm for a 1200V rated NPT-IGBT has not been realized up to now.

(19) The “breakdown voltage” V.sub.bd may be defined as the voltage at which a specific semiconductor device breaks down due for example to avalanche effects.

(20) An idea of the present invention may be to provide a new design rule for non-punch-through semiconductor devices, particularly for reverse conducting RC-IGBTs, while at the same time improving the electrical performance of the conventional NPT-IGBTs. The new design rule may be particularly advantageous for application on power semiconductor devices rated below 2000 V as such relatively low rated power semiconductor devices typically comprise thin semiconductor wafers and can benefit more from an NPT structure compared to higher voltage rated devices.

(21) According to an aspect of the present invention, a non-punch-through reverse conducting semiconductor device comprising a four-layer structure with reduced thickness is proposed, wherein the four-layer structure comprises: (1) a collector on a collector side of the semiconductor device including an optimized pattern of alternating p-type doped and n-type doped regions; (2) an emitter on an emitter side, which lies opposite to the collector side; (3) a base layer arranged between the emitter and the collector; and (4) a low doped bipolar gain control (BGC) layer arranged between the base layer and the collector. Therein, the base layer preferably may have a substantially constant doping concentration, meaning that the doping concentration is substantially homogeneous throughout the base layer. The low doped bipolar gain control (BGC) layer has a peak doping concentration which is equal or higher than the doping concentration of the base layer.

(22) As special features, (1) the doping concentration of the base layer and a thickness of the base layer are selected such that at the breakdown voltage V.sub.bd of the semiconductor device, the length of the “space charge free (SCF) zone” (i.e. the distance from the end of the electric field (or space charge) region to the collector side) is reduced to below 15% of the total device thickness, and (2) the electric field (or space charge) region does not reach the low doped bipolar gain control (BGC) layer which is entirely located in the “space charge free (SCF) zone”.

(23) The thickness of the space charge region at a specific reverse voltage and the breakdown voltage of the semiconductor device strongly depend upon a doping concentration within the base layer of the device. The proposed new design rule includes a selection range on the thickness of the base layer for a non-punch-through semiconductor device depending on the doping concentration of the base layer.

(24) The proposed new design is specifically applicable for power semiconductor devices such as IGBTs and in particular RC-IGBTs processed on thin wafers rated below 2000 V with target thicknesses much lower than showed possible in the paper Optimizing the Vertical IGBT Structure—The NPT Concept as the Most Economic and Electrically Ideal Solution for a 1200V-IGBT by T. Laska et. al.

(25) For example, the new design may be applied to a 1200 V RC-IGBT and may result in a non-punch-through device thickness below 160 μm compared to the state-of-the-art 170 μm to 180 μm. This means that an NPT RC-IGBT can achieve comparable or even better performance than punch-through IGBTs, at lower manufacturing costs and complexity. The proposed design rule may allow the device to maintain similar losses as prevailing in conventional punch through designs with a higher or similar blocking capability. The new design rule may also benefit from softer turn-off characteristics, and higher temperature of operation due to the severe limitations in leakage current for conventional NPT-IGBT which lead to the thermal runaway of the semiconductor device.

(26) To allow for thickness reductions for an NPT device with an n-type base layer, a reduction of the pnp bipolar gain is necessary. This is achieved with a combination of (1) a shorted collector pattern of alternating p-type doped and n-type doped regions and (2) a low n-type doped bipolar gain control BGC layer located in its entirety in the SCF zone. The BGC layer main task is to provide a lower bipolar gain for a reduced leakage current in the reverse blocking state and stable reverse blocking characteristics statically and dynamically.

(27) The peak doping concentration of the BGC layer may be below 1×10.sup.16 cm.sup.−3, preferably below 5×10.sup.15 cm.sup.−3 and more preferably below 1×10.sup.15 cm.sup.−3. Accordingly, the peak doping concentration of the BGC layer may be lower than in conventional punch-through semiconductor devices since it is not required to perform as a buffer layer or field stop layer. The low doped BGC layer will provide good on-state IV performance with minimum snap-back for improved current sharing between parallel devices during switching.

(28) The BGC layer may have a thickness ranging between 1 μm and 10 μm, preferably between 1 μm and 5 μm and more preferably between 1 μm and 3 μm. As the thickness of the BGC layer according to the invention may be significantly thinner than in conventional punch through semiconductor devices, it may be easier to be produced using for example ion implantation or proton irradiation defect engineering techniques.

(29) Advantageously, the doping concentration of the base layer, and a thickness of the base layer are adapted such that the space charge free (SCF) zone at V.sub.bd is smaller than 15%, preferably smaller than 10%, and more preferably smaller than 5%.

(30) Advantageously, the proposed new design may be applied to semiconductor devices in which the doping concentration of the base layer, and a thickness of the base layer are adapted such that the breakdown voltage V.sub.bd of the semiconductor device is below 2500 V, preferably below 2200 V and more preferably below 2000 V. As the rated voltage V.sub.rating of a semiconductor device is usually defined as being sufficiently below the breakdown voltage of the device, this may correspond to the semiconductor device having a rated voltage being for example smaller than 1800 V. As already indicated above, the proposed new design may be specifically suitable for such relatively low rated semiconductor devices. A reason may lie in the fact that for such devices, the use of a buffer or field-stop layer for thin wafers is very complicated from the processing perspective, and affects device performance parameters such as ruggedness and softness. Furthermore, applying the new design rule for higher voltage devices may not lead to substantial advantages due to the much lower base region doping concentrations employed for such devices.

(31) According to a further aspect of the present invention, a method for producing a thin non-punch-through reverse conducting Insulated gate bipolar transistor NPT RC-IGBT comprising a four-layer structure with layers of different conductivity types is proposed. The method comprises production steps being preferably performed in the following order: (a) providing a wafer of a first conductivity type, which comprises a first side which is the emitter side in the finalized semiconductor device, and a second side lying opposite the first side; (b) performing steps for producing an emitter layer on the first side; (c) thinning down the wafer by mechanical grinding and/or etching to reduce its thickness to the desired value, as indicated by the target breakdown voltage of the device; and (d) applying particles of a first and second conductivity type to the wafer on its second side by implantation or deposition, which particles form a pattern of alternate p-type doped and n-type doped regions on the collector layer to form a shorted collector in the finalized reverse conducting semiconductor device; and (e) applying particles or donor defects by using implantation or proton irradiation and subsequent annealing to form a bipolar gain control layer of the first conductivity type located in the space charge free zone.

(32) Accordingly, when the method is adapted for producing an RC-IGBT, in step (d), p-type particles such as Boron (B) may be implanted uniformly with a dose higher than 1×10.sup.12 cm.sup.−2, preferably higher than 5×10.sup.12 cm.sup.−2, and more preferably above 1×10.sup.13 cm.sup.−2 and with energies higher than 10 keV, preferably higher than 25 keV, and more preferably above 50 keV. Accordingly, n-type particles such as Phosphorus (P) may be implanted with a predefined pattern with a dose higher than 1×10.sup.14 cm.sup.−2, preferably higher than 5×10.sup.14 cm.sup.−2, and more preferably above 1×10.sup.15 cm.sup.−2 and with energies higher than 50 keV, preferably higher than 100 keV, and more preferably higher than 120 keV to ensure full compensation of the p-type regions and a suitable pattern of alternate p-type doped and n-type doped regions will be created on the collector side. The predefined pattern can be of different layout design concepts such as cellular, short or long stripes and/or other variations. The dimension of the p-type doped regions is more than 50 um, preferably above 100 um, and more preferably above 200 um. The dimension of the n-type doped regions is 10 um, preferably above 50 um, and more preferably above 100 um. The dimension of the p-type doped region is equal or larger than the dimension of the n-type doped region. After step (d), an annealing step may be performed, wherein the annealing step comprises thermal annealing at temperatures below 500° C., preferably below 450° C. Alternatively, the annealing step may be performed by a laser annealing to achieve higher dopant activation levels.

(33) Accordingly, when the method is adapted for producing the BGC layer for the RC-IGBT, in step (e), n-type particles such as Phosphorus (P) may be implanted uniformly with a dose lower than 5×10.sup.12 cm.sup.−2, preferably lower than 1×10.sup.12 cm.sup.−2, and more preferably lower than 5×10.sup.11 cm.sup.−2 and with energies higher than 100 keV, preferably higher than 150 keV, and more preferably above 200 keV. After step (e), an annealing step may be performed, wherein the annealing step comprises thermal annealing at temperatures below 500° C. Alternatively, the annealing step may be performed by a laser annealing to achieve higher dopant activation levels. The activation can be done at the same step as for step (d) or separately.

(34) Alternatively, when the method is adapted for producing the BGC layer for the RC-IGBT, in step (e), particles such as Hydrogen (H) (i.e. proton) may be implanted or irradiated uniformly with a dose lower than 1×10.sup.15 cm.sup.−2, preferably lower than 1×10.sup.14 cm.sup.−2, and more preferably lower than 5×10.sup.13 cm.sup.−2 and with energies higher than 100 keV, preferably higher than 200 keV, and more preferably above 300 keV. After step (e), an annealing step may be performed, wherein the annealing step comprises thermal annealing at temperatures below 450° C. The activation can be done after step (d) is completed if laser anneal is performed for step (d).

(35) It has to be noted that aspects and embodiments of the present invention are described herein with reference to different subject-matters. In particular, some embodiments are described with reference to the method type claims whereas other embodiments are described with reference to apparatus type claims. However, a person skilled in the art will gather from the above and the following description that, unless other notified, in addition to any combination of features belonging to one type of subject-matter also any combination between features relating to different subject-matters, in particular between features of the apparatus type claims and features of the method type claims, is considered to be disclosed with this application.

(36) FIG. 5, element b, shows a semiconductor device according to an embodiment of the invention. The standard non-punch-through semiconductor device is represented in FIG. 1, element a, as an NPT-IGBT 10. It comprises a three-layer structure having a collector side 21 and an emitter side 31 lying opposite to the collector side 21. The layers provided on the emitter side 31 typically comprise a p-type doped channel region 1 which surrounds an n-type doped source region 11. These regions 1, 11 are in electrical contact with an emitter electrode 3. A gate electrode 12 is manufactured on top of the wafer, electrically insulated from the layers 1, 11 by a gate insulation layer 14 for forming the channel and electrically insulated from the emitter electrode 3 by an insulating layer 13.

(37) A base layer 4 is located between the emitter 3 and the collector 2.

(38) On the collector side 21, a collector metallization 2 is formed in contact with collector layer 6 which is formed in the finalized semiconductor device 10 by implantation or deposition of p-type particles.

(39) The standard punch-through device is represented in FIG. 1, element b, as a PT-IGBT 20 which includes an additional n-type doped buffer layer or field stop 5. Due to the buffer layer 5, the thickness of the PT-IGBT is much reduced compared to the NPT-IGBT. FIG. 2 shows the corresponding doping concentration profile and electrical field at V.sub.bd for both NPT and PT devices. For the NPT-IGBT 10, the electric field (space charge region) edge 50 at V.sub.bd ensures a wide space charge free SCF zone (un-depleted zone) in the base region 4. For a PT-IGBT, the SCF zone is located in the buffer layer 5.

(40) To control the collector injection efficiency or integrate a freewheeling diode in the same IGBT device, a shorted collector CS design is employed for both NPT CS-IGBT 100 (or NPT RC-IGBT) 100 and PT CS-IGBT 200 (or PT RC-IGBT). FIG. 3 shows the cross section of both devices which includes an additional n-type doped short region 8. FIG. 4 shows the corresponding doping concentration profile and electrical field at V.sub.bd for both NPT And PT devices with collector shorts 8.

(41) For both NPT and PT devices, the pnp bipolar gain β.sub.pnp can be calculated using

(42) ${\beta }_{PNP}=\frac{n_{iSCF}^2}{n_{iC}^2}.Math.\frac{D_{pSCF}}{D_{nC}}.Math.\frac{L_{nC}}{W_{SCF}}.Math.\frac{N_{AC}}{N_{DSCF}}$
Where W.sub.SCF is the width of the SCF zone, N.sub.DSCF and N.sub.AC represent the background doping of the SCF zone and the IGBT p-type collector 6 respectively. Also, D.sub.pSCF and D.sub.nC are the minority carrier diffusion coefficients in the SCF zone and collector 6 respectively. Finally, L.sub.nC is the diffusion length of electrons in the collector 6.

(43) A narrower W.sub.SCF, lower N.sub.DSCF and/or higher N.sub.AC values will result in increased gain levels having the drawback of increased leakage currents.

(44) Therefore, due to the absence of a buffer layer 5, the NPT-IGBT 10 requires wide W.sub.SCF to enable 125° C. operating temperature capability albeit with increase losses. Furthermore, this presents a clear limit to reduce the NPT device thickness while operating at even higher temperatures.

(45) Hence, the addition of a buffer layer 5 as for PT-IGBT 20 will result in lower leakage currents especially at higher temperatures. Furthermore, the addition of collector shorts 8 will also result in reduced injection efficiency and can contribute to a higher value for N.sub.DSCF for a reduced β.sub.pnp.

(46) In the past, the following equation was used to calculate the optimum thickness of a NPT-IGBT:

(47) $W_{NPT}\left(\mathrm{\mu m}\right)=V_{rating}\left(V\right)\times \left(0.15\mathrm{to}0.166\right)\left(\frac{\mathrm{\mu m}}{V}\right)$
The device breakdown voltage can be calculated as follows

(48) $V_{\mathrm{bd}}\left(V\right)=\frac{{\mathrm{.Math.}}_s{E}_c^2}{2q{N}_{DB}}=\frac{1.31\times 10^{17}\left(\frac{V}{{\mathrm{cm}}^3}\right)}{N_{DB}\left(\frac{1}{{\mathrm{cm}}^3}\right)}$
Where ε.sub.s is the permittivity of silicon and equal to 1.05×10.sup.−12 F/cm, q is the electron charge and equal to 1.602×10.sup.−19 C, E.sub.c is the critical electric field and assumed here to be 2×10.sup.5 V/cm and N.sub.DB is the doping concentration of the base region 4.

(49) The width of the space charge region W.sub.scr at V.sub.bd is given as

(50) $W_{scr}\left(\mu m\right)=\frac{2V_{\mathrm{bd}}}{E_c}=V_{\mathrm{bd}}\left(V\right)\times 0.1\left(\frac{\mathrm{\mu m}}{V}\right)$
Hence, the space charge free (SCF) zone can be calculated as

(51) $W_{SCF}\left(\mathrm{\mu m}\right)=W_{NPT}\left(\mathrm{\mu m}\right)-W_{\mathrm{scr}}\left(\mathrm{\mu m}\right)=\left(0.15\mathrm{to}0.166\right)\left(\frac{\mathrm{\mu m}}{V}\right)\times V_{\mathrm{rating}}\left(V\right)-0.1\left(\frac{\mathrm{\mu m}}{V}\right)\times V_{bd}\left(V\right)$

(52) FIG. 5, element b, schematically shows a typical cross section for a thin non-punch-through semiconductor device or thin NPT RC-IGBT 300 in accordance with an embodiment of the present invention. On the emitter side 31, the doping profile of the p-type layer 1 and of the adjacent n-type base layer 4 is similar to the case of a prior art non-punch-through or punch-through semiconductor device. However, as can be easily derived by comparing with FIG. 3a for a prior-art NPT RC-IGBT 100, the thickness of the base layer is significantly reduced. A predefined collector short pattern of alternate p-type doped 6 and n-type doped 8 regions are introduced on the collector side 21. FIGS. 7, 8 and 9 shows plan views of the different collector short patterns for the thin NPT RC-IGBT according to the invention. Typical designs for the collector short pattern are a cellular design (as shown in FIG. 7) or a stretched cellular design (as shown in FIG. 8), or a stripe design (as shown in FIG. 9).

(53) Additionally, to increase N.sub.DSCF for obtaining a lower W.sub.SCF and therefore a lower pnp bipolar gain, an n-type low doped bipolar gain control BGC layer 9 may be implemented into the second side of the wafer 21. The BGC layer 9 is located in its entirety in the SCF zone close to the collector side 21. FIG. 6, element b, shows the location of the BGC layer 9 in the SCF zone. A distance 7 may separate the edge of the electric field 50 (space charge region) at V.sub.bd from the BGC layer 9.

(54) The combination of the collector shorts 8 and BGC layer 9 allows substantial reductions in the pnp bipolar gain levels and hence a thinner NPT RC-IGBT design can be realized based on the following equation

(55) $W_{NPT-RC}\left(\mathrm{\mu m}\right)=V_{rating}\left(V\right)\times \left(0.125\mathrm{to}0.133\right)\left(\frac{\mathrm{\mu m}}{V}\right)$
Hence, the space charge free (SCF) zone 300 in accordance with an embodiment of the present invention can be given as

(56) $W_{SCF}\left(\mathrm{\mu m}\right)=W_{NPT-RC}\left(\mathrm{\mu m}\right)-W_{\mathrm{scr}}\left(\mathrm{\mu m}\right)=\left(0.125\mathrm{to}0.133\right)\left(\frac{\mathrm{\mu m}}{V}\right)\times V_{\mathrm{rati}ng}\left(V\right)-0.1\left(\frac{\mathrm{\mu m}}{V}\right)\times V_{bd}\left(V\right)$
Based on the above equations, Table 1 was obtained showing both the prior-art NPT IGBT 10 and NPT RC-IGBT 100 designs for 600 V, 900 V, 1200 V, and 1700 V and a thin NPT RC-IGBT 300 in accordance with the present invention. The table includes the design parameters and relevant ratios while utilizing (0.158V.sub.rating) for calculating W.sub.NPT for prior art devices and (0.129V.sub.rating) for calculating W.sub.NPT-RC for the device in accordance with the present invention.

(57) For example, while the thickness of the conventional NPT device rated at 1200V may be above 180 μm, the thickness of the new NPT device may be less than 160 μm.

(58) TABLE-US-00001 TABLE 1 Prior Art NPT-IGBT and NPT RC-IGBT V.sub.rating V 600 900 1200 1700 V.sub.bd (including 15% margin) V 690 1035 1380 1955 W.sub.NPT μm 95 142 190 269 W.sub.SCR μm 69 103.5 138 195.5 W.sub.SCF μm 26 39 52 73 W.sub.SCF/W.sub.NPT % 27% 27% 27% 27% N.sub.DB atom/cm.sup.3 1.90E+14 1.27E+14 9.49E+13 6.70E+13 Base Resistivity ohm .Math. cm 23 34 46 64 Base Resistivity ohm .Math. cm 26 39 53 74 with 15% margin Thin NPT RC-IGBT in accordance with the new invention V.sub.rating V 600 900 1200 1700 V.sub.bd V 690 1035 1380 1955 W.sub.NPT-RC μm 77 116 155 219 W.sub.SCR μm 69 103.5 138 195.5 W.sub.SCF μm 8 13 17 24 W.sub.SCF/W.sub.NPT-RC % 11% 11% 11% 11% N.sub.DB atom/cm.sup.3 1.90E+14 1.27E+14 9.49E+13 6.70E+13 Base Resistivity ohm .Math. cm 23 34 46 64 Base Resistivity ohm .Math. cm 26 39 53 74 with 15% margin

(59) FIG. 10 shows a graph representing the blocking characteristics (collector leakage current I.sub.c versus the collector emitter voltage V.sub.ce) at 125° C. for 1200V rated devices. The graph depicts the blocking characteristics of a conventional non-punch-through NPT IGBT 10 with a device thickness of (A) 185 μm, (B) 175 μm (C) 165 μm and (D) 155 μm, along with conventional NPT RC-IGBT 100 with a thickness of 185 μm (F). A conventional punch-through PT-IGBT 20 with a thickness of 130 μm (E) is also included for reference. The curves are compared to the blocking characteristic of a thin NPT RC IGBT 300 in accordance with the present invention, with a thickness of 155 μm (G) and a BGC layer doping concentration equal to N.sub.BD. The conventional NPT-IGBT 10 shows clear limitations even for the 185 μm state-of-the-art design. Both conventional PT-IGBT 20 and NPT RC-IGBT 100 show low leakage levels with the thin NPT RC-IGBT 300 maintaining good performance up to 1200V even with the minimum BGCL doping level. The NPT RC-IGBT 300 has similar conduction voltage drop V.sub.ce(sat) at 100 A/cm.sup.2 to the PT-IGBT 20 and 15% lower than the conventional thicker device 100. Furthermore, the NPT RC-IGBT 300 has 15% lower turn-off losses than the conventional thicker device 100.

(60) FIG. 11 shows a graph representing the blocking characteristics (collector leakage current I.sub.c versus the collector emitter voltage V.sub.ce) at 200° C. for 1200V rated devices. The graph depicts the blocking characteristic of a conventional punch-through IGBT 20 with a device thickness of (E) 130 μm. The curves include the thin NPT RC IGBT 300 in accordance with the present invention, with a thickness of 155 μm, having a 2 μm thick BGC layer with peak doping concentrations of (G) equal to N.sub.BD, (H) 5×10.sup.14 cm.sup.−3, (I) 1×10.sup.15 cm.sup.−3, (J) 5×10.sup.15 cm.sup.−3, and (K) 1×10.sup.16 cm.sup.−3. It is clear that depending on the application requirements, the new design can be adjusted to match the target performance by adjusting the BGC layer doping concentration.

(61) In order to produce a thin non-punch-through semiconductor device according to an exemplary embodiment of the present invention, an n-type wafer with a resistivity of for example 53 ohm.Math.cm for a 1200V device (a base doping concentration of 8.15×10.sup.13 cm.sup.−3 may be provided as a substrate as shown in FIG. 12, element a. On a first side which, in the finalized semiconductor device forms the emitter side, one or more layers for forming an emitter structure may be produced for example by diffusion processes as shown in FIG. 12, element b. Then, the wafer which originally may have a thickness of for example more than 300 μm may be thinned on its second side to a predetermined thickness of for example 160 μm as shown in FIG. 12, element c. This may be done for example by grinding, and etching 40. For the specific case of producing an RC-IGBT, the collector or anode design 6 using a uniform implantation of p-type dopants 60 such as boron is performed as shown in FIG. 13, element a. Also, a thin p-type silicon layer may be deposited on the collector side of the wafer. Then, the n-type short 8 is performed using implantation of n-type dopants such as phosphorus 70 is through a predefined pattern on a mask as shown in FIG. 13, element b. The much higher dose of the phosphorus will ensure full compensation of the p-type collector in the short regions. The collector 6 and short 8 regions dopants are activated by low temperature annealing below 500° C. or laser annealing may be applied.

(62) For the low doped n-type BGC layer 9, n-type particles such as phosphor or arsenic atoms may be implanted and activated with the collector 6 and short regions as shown in FIG. 13, element c. Alternatively, hydrogen atoms may be implanted followed by a low temperature annealing below 450° C.

(63) Finally, the collector metallization 2 is performed to obtain the finished thin NPT RC-IGBT 300 device in accordance to the present invention as shown in FIG. 14.

(64) The thin NPT RC-IGBT 300 according to the present invention design proposed herein may be applied to all types of IGBT cell designs including enhanced planar IGBTs 301 with an n-type doped enhancement layer 15 surrounding the p-type channel layer 1 as shown in FIG. 15 and trench IGBTs 302 as shown in FIG. 16, as well as enhanced trench IGBTs or other combinations of planar and trench cell designs.

(65) It should be noted that the term “comprising” does not exclude other elements or steps and that the indefinite article “a” or “an” does not exclude the plural. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.