Device and method of median filtering

Abstract

A median filter device is provided with a reordered circuit, a comparison circuit and a data refresh circuit on the basis of the conventional data buffer circuit and data register circuit. The reorder circuit re-sorts the signal data stored in the data buffer circuit in a preceding clock cycle according to their numerical values. The comparison circuit compares the new signal datum entered in the current clock cycle with the signal data already stored to generate a median. The data refresh circuit updates the signal codes stored in the data register circuit with the signal codes corresponding to the new signal data, for calculation of the median in a following clock cycle. The length of the data buffer circuit and data register circuit can be reduced from N signal data to N1 signal data, which achieves less data storage capacity, smaller circuit area, easier data processing and higher operation efficiency.

Claims

1. A median filter device to obtain a middle value of N signal data stored therein in each clock cycle, wherein N is an odd number greater than 1; the median filter device comprises: a data buffer circuit with a length of N1 signal data, for storing last N1 signal data of a sequence of signal data sequentially received by the median filter device during a preceding clock cycle, wherein each signal data has a numerical value; a data encoding circuit with a length of N1 signal data, for encoding the signal data stored in the data buffer circuit into signal codes according to the numerical values of the signal data; a reorder circuit connected with the data buffer circuit and the data encoding circuit, for sorting all the signal data stored in the data buffer circuit according to their corresponding signal codes from small to large or large to small to obtain a sequence of reordered signal data; a comparison circuit connected with the reorder circuit, for comparing a new signal datum entering the median filter device in the current clock cycle with the N1 signal data in the sequence of the reordered signal data, and inserting the new signal datum into the sequence of the reordered signal data according to the numerical value of the new signal datum to form a new signal data sequence of N signal data stored in the median filter device in the current clock cycle from large to small or small to large, and generating a median of the N signal data stored in the median filter device in the current clock cycle; and a data refresh circuit connected with the comparison circuit and the data encoding circuit, for encoding rest N1 signal data except for signal data to leave the median filter device in the current clock cycle into new signal codes according to their numerical values, and updating the signal codes stored in the data encoding circuit with the new signal codes according to the entry sequence of the rest N1 signal data.

2. The median filter device according to claim 1, wherein the comparison circuit further performs positional encoding to each position adjacent to each of the reordered N1 signal data into a positional code to obtain N1 positional codes of positions where the new signal datum to be inserted, wherein two positions adjacent to the signal datum to leave the median filter device are encoded to have a same positional code; the comparison circuit compares the new signal datum with the N1 signal data of the sequence of the reordered signal data, and inserts the new signal datum into a corresponding position in the sequence, so as to form a new signal data sequence of N signal data from large to small or small to large; the comparison circuit further takes the numerical value of a signal datum ranked at (N1)/2+1 in the new signal data sequence as the median.

3. The median filter device according to claim 2, wherein the comparison circuit encodes the positions of the signal data based on binary format.

4. The median filter device according to claim 1, wherein the data buffer circuit removes the signal datum to leave in the current clock cycle and adds the new entered signal datum in the current clock cycle, and stores N1 signal data for a following clock cycle.

5. The median filter device according to claim 1, wherein the data encoding circuit encodes the signal data based on binary format, decimal format, or hexadecimal format.

6. A median filter method using a median filter device according to claim 1 to obtain a middle value of N signal data stored therein in each clock cycle, wherein N is an odd number greater than 1; the median filter method comprises the following steps: S01, in a preceding clock cycle, storing last N1 signal data of a sequence of signal data sequentially entering the median filter device by the data buffer circuit; encoding the signal data stored in the data buffer circuit into signal codes by the data encoding circuit according to numerical values of the signal data; sorting all the signal data stored in the data buffer circuit according to their corresponding signal codes from small to large or large to small by the reorder circuit to obtain a sequence of reordered signal data; S02, in a current clock cycle, receiving a new signal datum by the median filter device; S03, comparing the new signal datum with the N1 signal data in the sequence of the reordered signal data, inserting the new signal datum into the sequence of the reordered signal data according to the numerical value of the new signal datum to form a new signal data sequence of N signal data from large to small or small to large stored in the median filter device in the current clock cycle, and generating a median of the N signal data stored in the median filter device in the current clock cycle, by the comparison circuit; S04, encoding rest N1 signal data except for a signal datum to leave the median filter device in the current clock cycle into new signal codes according to their numerical values, and updating the signal codes stored in the data encoding circuit with the new signal codes according to the entry sequence of the rest N1 signal data, by the data refresh circuit; S05, removing the signal to leave the median filter device.

7. The median filter method according to claim 6, wherein, step S03 further comprises: performing positional encoding to each position adjacent to each of the reordered N1 signal data into a positional code to obtain N1 positional codes of positions where the new signal datum to be inserted, wherein two positions adjacent to the signal datum to leave the median filter device are encoded to have a same positional code; comparing the new signal datum with the N1 signal data of the sequence of the reordered signal data, and inserting the new signal datum into a corresponding position in the sequence, so as to form a new signal data sequence of N signal data from large to small or small to large; taking the numerical value of a signal datum ranked at (N1)/2+1 in the new signal data sequence as the median.

8. The median filter method according to claim 6, wherein, step S05 further comprises removing the signal datum to leave the median filter device in the current clock cycle from the data buffer circuit and adding the new entered signal datum in the current clock cycle into the data buffer circuit, and storing N1 signal data for a following clock cycle in the data buffer circuit.

9. The median filter method according to claim 6, wherein the data encoding circuit encodes the signal data based on binary format, decimal format, or hexadecimal format.

10. The median filter method according to claim 7, wherein the comparison circuit encodes the positions of the signal data based on binary format.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram of the median filter device of the present invention;

(2) FIG. 2 is a flow chart of the median filter method of the present invention;

(3) FIG. 3 is a diagram showing the comparison circuit processing the new signal datum;

(4) FIG. 4 is a diagram showing signal data process in a clock cycle according to a first embodiment of the present invention;

(5) FIG. 5 is a diagram showing signal data process in a following clock cycle according to the first embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(6) The embodiments of the present invention will now be descried more fully hereinafter with reference to the accompanying drawings. It should be appreciated that the specific embodiments disclosed might be readily utilized as a basis for modifying or designing other structures or processes for carrying out the purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions and variations on the example embodiments described do not depart from the spirit and scope of the invention as set forth in the appended claims. The figures are not necessarily drawn to scale, should be understood to provide a representation of particular embodiments of the invention, and are merely conceptual in nature and illustrative of the principles involved.

(7) Please refer to FIG. 1, in the present invention, the median filter device to obtain a median of N signal data stored in it in each clock cycle comprises a data buffer circuit, a data register circuit, a reorder circuit, a comparison circuit and a data refresh circuit.

(8) The data buffer circuit 1 has a length of N1 signal data, meaning a storage capacity of N1 signal data, to store a sequence of last N1 signal data sequentially received by the median filter device in a preceding clock cycle, represented by D.sub.N-2, D.sub.N-3, . . . , D.sub.2, D.sub.1, D.sub.0. Wherein, D.sub.0 is the first signal data in the data buffer circuit, D.sub.N-2 is the last signal data in the data buffer circuit.

(9) The data register circuit 2 has a length of N1 signal data, meaning a storage capacity of N1 signal data, to store signal codes corresponding to numerical values of the signal data in the data buffer circuit in the same sequence as the entry sequence of these signal data, represented by C.sub.N-2, C.sub.N-3, . . . , C.sub.2, C.sub.1, C.sub.0 herein. Wherein, C.sub.N-2, C.sub.N-3, . . . , C.sub.2, C.sub.1, C.sub.0 are signal codes corresponding to the signal data D.sub.N-2, D.sub.N-3, . . . , D.sub.2, D.sub.1, D.sub.0 stored in the data buffer circuit.

(10) The term signal code is a code which reflects the numerical value of each signal data. For example, the signal codes can be decimal codes like 0, 1, 2, . . . N1. In practical application, the signal codes also be binary codes or hexadecimal codes.

(11) The reorder circuit 3 is respectively connected with the data buffer circuit 1 and the data register circuit 2, for sorting all the signal data stored in the data buffer circuit 1 from small to large or large to small according to their corresponding signal codes in the data register circuit 2, so as to obtain a sequence of reordered signal data, represented by DS.sub.N-2, DS.sub.N-3, . . . , DS.sub.2, DS.sub.1, DS.sub.0; wherein DS.sub.N-2DS.sub.N-3 . . . DS.sub.2DS.sub.1DS.sub.0.

(12) The comparison circuit 4 is connected with the reorder circuit 3, for comparing a new signal datum DIN entering the median filter device in the current clock cycle with the reordered signal data, forming a new signal data sequence of N signal data and generating a median of the N signal data in the current clock cycle.

(13) The data refresh circuit 5 is respectively connected with the comparison circuit 4 and the data register circuit 2, for encoding rest N1 signal data except for the signal datum D.sub.0 to leave the median filter device in the current clock cycle into new signal codes according to their numerical values, and updating the signal codes stored in the data register circuit 2 with the new signal codes in the same sequence as the entry sequence of the rest N1 signal data, so as to obtain N1 new signal codes C.sub.N-2, C.sub.N-3, . . . , C.sub.2, C.sub.1, C.sub.0 corresponding to the numerical values of the signal data DIN, D.sub.N-2, D.sub.N-3, . . . , D.sub.2, D.sub.1. Wherein, N is an odd number greater than 1.

(14) Please refer to FIG. 2, the median filter method using the above median filter device to obtain a middle value of N signal data stored therein in each clock cycle comprises the following steps:

(15) S01, in a preceding clock cycle, the data buffer circuit storing last N1 signal data of a sequence of signal data sequentially received by the median filter device; the data register circuit storing N1 signal codes corresponding to numerical values of the signal data in the data buffer circuit in the same sequence as the entry sequence of these signal data; the reorder circuit sorting all the signal data stored in the data buffer circuit 1 from small to large or large to small according to their corresponding signal codes, so as to obtain a sequence of reordered signal data;

(16) S02, in a current clock cycle, a new signal datum entering the median filter device;

(17) S03, the comparison circuit comparing the new signal datum with the N1 reordered signal data, forming a new signal data sequence of N signal data in the current clock cycle, and generating a median of the N signal data;

(18) S04, the data refresh circuit encoding rest N1 signal data except for a signal datum to leave the median filter device (the first signal data entering the median filter device in the current clock cycle) in the current clock cycle into new signal codes according to their numerical values, and updating the signal codes stored in the data register circuit with the new signal codes in the same sequence with the entry sequence of the rest N1 signal data.

(19) S05, the first entered signal datum leaving the median filter device.

(20) Wherein, step S03 is preferably implemented in the following way:

(21) The comparison circuit performs positional encoding to each position adjacent to each of the reordered N1 signal data into a positional code. Wherein two positions adjacent to the signal datum to leave the median filter device are encoded to have a same positional code, such that N1 positional codes of positions where the new signal datum can be inserted are obtained. Then, the comparison circuit compares the new signal datum entering the median filter device with the N1 reordered signal data, and inserts the new signal datum into the reordered signal data to form a new signal data sequence of N signal data and generates the median of the N signal data. Specifically, as shown in FIG. 3, in the sequence of reordered signal data DS.sub.N-2, DS.sub.N-3, . . . , DS.sub.2, DS.sub.1, DS.sub.0, the positions between each two adjacent reordered signal data and the positions at two ends of the sequence of the reordered signal data are all positional encoded. These positions can be inserted by the new signal datum. Assuming that the signal datum to leave is DS.sub.2, two positions adjacent to signal datum DS.sub.2 are encoded to have a same positional code, and all the positional codes are represented as S.sub.N-1, S.sub.N-2, . . . , S.sub.2, S.sub.1, S.sub.0. Wherein, S.sub.N-1 represents a position where the new signal datum DIN is inserted before the signal data DS.sub.N-2 (DINDSN2), S.sub.4 represents a position where the new signal datum DIN is inserted between the signal data DS.sub.4 and DS.sub.3 (DS.sub.4>DINDS.sub.3), S.sub.3 represents a position where the new signal datum DIN is inserted between the signal data DS.sub.3 and DS.sub.4 (DS.sub.3>DINDS.sub.2), S.sub.2 represents a position where the new signal datum DIN is inserted between the signal data DS.sub.2 and DS.sub.1 (DS.sub.2>DINDS.sub.1), S.sub.1 represents a position where the new signal datum DIN is inserted between the signal data DS.sub.1 and DS.sub.0 (DS.sub.1>DINDS.sub.0), and S.sub.0 represents a position where the new signal datum DIN is inserted after the signal data DS.sub.0 (DS.sub.0>DIN). In the embodiment, the value of the positional codes are N2 . . . 3, 2, 1, 0. Therefore, for the insertion of the new signal datum, only N1 positional codes are required. Then, the comparison circuit compares the new signal datum with the N1 reordered signal data, and inserts the new signal datum to form a new signal data sequence of N signal data including the signal datum to leave. The numerical value of the signal datum ranked at (N1)/2+1 in the new signal data sequence is the median. Furthermore, step S050 further comprises removes the first entered signal datum from the data buffer circuit and adds the new signal datum into the data buffer circuit.

(22) Wherein, N is an odd number.

(23) The data process in a clock cycle and a following clock cycle will be described with reference to FIG. 4 and FIG. 5 as follows. Wherein, N equals to 5.

(24) As shown in FIG. 4, in a current clock cycle, the data buffer circuit has already stored four signal data FFH, B0H, 80H, 40H in the order of entry sequence. Wherein, the signal data 00H is removed from the data buffer circuit before the current clock cycle. The data register circuit encodes these four signal data into signal codes 3, 2, 1, 0 corresponding to the numerical values of the signal data and stored therein. The reorder circuit re-sorted these four signal data from large to small to form a new sequence of reordered signal data FFH, B0H, 80H, 40H.

(25) In the current clock cycle, a new signal datum A0H enters the median filter device. The comparison circuit encodes the positions adjacent to the signal data 40H which will leave the median filter device into a same binary code 00, and encodes the other positions adjacent to the other signal data in the new sequence from large to small into binary codes 11, 10 and 01. The comparison circuit compares the signal datum A0H with the four signal data and determines that the signal datum A0H should be inserted into the position with a positional code of 01. As a result, the new sequence of signal data is formed as FFH, B0H, A0H, 80H, 40H. The median is generated to be A0H.

(26) The data refresh circuit encodes rest four signal data FFH, B0H, A0H, 80H, except for the signal datum 40H to leave the median filter device, into four new signal codes corresponding to their numerical values, and updates the signal codes stored in data register circuit with the new signal codes 1, 3, 2, 0 in the same sequence as the entry sequence of the four signal data.

(27) Finally, the first entered signal data in the current clock cycle 40H leaves the median filter device as well as the data buffer circuit.

(28) As shown in FIG. 5, in a following clock cycle, the signal datum 80H is the signal datum to leave while the signal datum 75H is the new entered signal data. Similarly, the data buffer circuit stores the signal data A0H, FFH, B0H, 80H sequentially, and the data register circuit encodes these signal data sequentially into signal codes 1, 3, 2, 0.

(29) When the new signal datum 75H enters the median filter device, the comparison circuit compares the numerical value of it with that of the other four signal data, and inserts the signal data 75H into the position with a positional code 00. The new sequence of five signal data is formed as FFH, B0H, A0H, 80H, 75H. The median is generated to be A0H.

(30) When the signal data 80H leaves, the data refresh circuit updates the data register circuit with the signal codes 0, 1, 3, 2 corresponding to the rest four signal data in the same sequence as the entry sequence of the rest four signal data.

(31) Finally, the signal data 80H leaves the median filter device.

(32) While this invention has been particularly shown and described with references to preferred embodiments thereof. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. It will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.