Backside spacer structures for improved thermal performance

Abstract

Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

Claims

1. A method comprising: providing a substrate, including integrated circuit devices, having front and back sides; forming a seed layer on the back side of the substrate; forming vertical spacers spaced from each other, in rows and columns on the seed layer, each vertical spacer having a first end contacting the seed layer and a second end opposite the first end in a vertical direction from the seed layer, wherein forming the vertical spacers comprises: electroplating vertical structures on the seed layer through a mask layer; and removing exposed sections of the seed layer, exposing sections of the back side of the substrate; providing a plate parallel to and spaced from the back side of the substrate; and forming a thermal interface material (TIM) layer, surrounding the vertical spacers, between the back side of the substrate and the plate, wherein every vertical spacer surrounded by the TIM layer extends from the first end to the second end with no intervening structure between the first end and the second end.

2. The method according to claim 1, comprising forming the vertical spacers to a height less than a thickness of the TIM layer.

3. The method according to claim 1, comprising forming the vertical spacers to a height connecting the back side of the substrate to the plate.

4. The method according to claim 1, comprising forming the vertical spacers based on properties of the TIM layer.

5. The method according to claim 1, comprising forming the vertical spacers having dimensions and spacing based on a thermal dissipation target associated with the substrate.

6. The method according to claim 1, comprising forming the vertical spacers of a metallic material.

7. The method according to claim 1, wherein the plate is a heat dissipating surface.

8. A method comprising: providing a substrate, including integrated circuit devices, having front and back sides; forming a seed layer on the back side of the substrate; forming metallic vertical spacers, on the seed layer, spaced from each other in rows and columns, each metallic vertical spacer having a first end contacting the seed layer and a second end opposite the first end in a vertical direction from the seed layer, wherein forming the vertical spacers comprises electroplating vertical structures on the seed layer through a mask layer; and removing exposed sections of the seed layer, exposing sections of the back side of the substrate; providing a plate parallel to and spaced from the back side of the substrate; and forming a thermal interface material (TIM) layer, surrounding the metallic vertical spacers, between the back side of the substrate and the plate, wherein every metallic vertical spacer surrounded by the TIM layer extends from the first end to the second end with no intervening structure between the first end and the second end.

9. The method according to claim 7, comprising forming the metallic vertical spacers having dimensions and spacing based on a thermal dissipation target associated with the substrate, properties of the TIM layer, or a combination thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

(2) FIGS. 1A through 1F illustrate cross sectional views of a process for forming spacers on a substrate in a TIM layer, in accordance with an exemplary embodiment; and

(3) FIGS. 1G through 1I illustrate three-dimensional views of spacers on a substrate in a TIM layer between the substrate and a lid, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

(4) For the purposes of clarity, in the following description, numerous specific details are set forth to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term about.

(5) The present disclosure addresses the problems of insufficient thermal conduction attendant upon using a conventional TIM layer between an IC substrate and a lid. The present disclosure addresses and solves such problems, for instance, by, inter alia, forming spacers, on the substrate in the TIM layer, to facilitate a more efficient heat transfer from the substrate to the lid.

(6) FIG. 1A illustrates a cross-sectional view of a substrate 101 having front and back sides, 103 and 105, respectively. The substrate includes integrated components and elements (not shown for illustrative convenience) forming an IC chip/die. The backside 105 may be a silicon (Si) substrate surface.

(7) In FIG. 1B, a seed layer 107 (e.g. copper) is formed (e.g. by sputter coating) on the backside of the substrate 101.

(8) As illustrated in FIG. 1C, spacers/studs 109 may be formed (e.g. by electroplating a metallic material such as copper), through openings in a photomask 111, on selective areas over the seed layer 107.

(9) In FIG. 1D, the photomask 111 is stripped. Exposed sections 113 of the seed layer 107 are then removed to expose sections of the backside 105 of the substrate 101, as illustrated in FIG. 1E. FIG. 1E illustrates the spacers 109 formed on the backside 105.

(10) As illustrated in FIG. 1F, the spacers 109 may be formed to have a same or different height and/or width and may be spaced at a same or different distance from each other.

(11) FIG. 1G illustrates a three-dimensional view of the spacers 109 formed, in rows and columns, on the backside 105 of the substrate 101. The spacers 109 may be formed to a height X 115. Solder balls 117 may be formed on a front-side 103 of the substrate 101, for example, to mount the IC chip onto an interface board.

(12) In FIG. 1H, a TIM layer 119 is formed/dispensed on the backside 105 of the substrate 101, to a height Y 121, surrounding the spacers 109.

(13) FIG. 1I illustrates a plate/lid 123 (e.g. part of an IC chip packaging) above and parallel to the TIM layer 119. A height S 125 between an upper surface of the spacers 109 and a lower surface of the lid 123 is the difference between the height Y 121 and the height X 115 of the spacers 109 (e.g. S=YX). The heat generated by the IC components in the substrate 101 may be transferred to the lid 123 (e.g. at height Y 121) through height X 115 of the spacers 109 and then through height S 125 in the TIM layer 119.

(14) As previously noted, the spacers 109 may also be formed to a full height (e.g. height Y) such that they connect to a lid 123 for a direct heat transfer from the substrate 101 to the lid 123. The metal spacers 109 reduce the thermal resistance between the substrate 101 and the lid 123. The thermal resistance may be further reduced (e.g. for a better heat transfer) by increasing the height of the spacers 109 (which decreases the thermal resistance of the spacers). For example, an increase in height from zero to the full thickness of the TIM can yield a 34% decrease in the thermal resistance.

(15) Dimensions and spacing of the spacers 109 may be based on the material used to form the spacers 109, characteristics/properties of the TIM layer 119, the thermal dissipation target associated with the substrate 101, or the like criteria. For example, increasing the metal density from zero to 64% can yield a 14% decrease in the thermal resistance.

(16) The embodiments of the present disclosure can achieve several technical effects including improved thermal performance of an IC package by forming spacers (e.g. heat transfer pipes) on a backside of an IC chip to reduce the thermal resistance of a TIM layer and provide a more efficient heat transfer from the IC chip to a lid. A thinner TIM layer may be used without a need for complex lid designs in 2D, 2.5D, and 3D IC packages. Furthermore, the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use SRAM cells (e.g., liquid crystal display (LCD) drivers, digital processors, etc.)

(17) In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.