Semiconductor device

Abstract

A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.

Claims

1. A semiconductor device comprising: a silicon substrate; a Through-Silicon Via (TSV) penetrating through the silicon substrate from a rear surface of the silicon substrate to a front surface of the silicon substrate; a first low relative permittivity film disposed over the front surface of the silicon substrate; a second low relative permittivity film disposed over the first low relative permittivity film; a contact layer disposed over the front surface of the silicon substrate and between the silicon substrate and the first low relative permittivity film; a semiconductor element disposed in the silicon substrate; a seal ring disposed surrounding the TSV in a plan view, a wiring layer connected to the semiconductor element through the contact layer; a TSV electrode disposed in the TSV to extend through the contact layer from the rear surface of the silicon substrate; a metal electrode disposed over the second low relative permittivity film; and one or more wiring layers that connect the metal electrode to the TSV electrode, extend through the first low relative permittivity film and the second low relative permittivity film, and are surrounded by the seal ring, wherein the first low relative permittivity film is the closest low relative permittivity film to the silicon substrate, and the second low relative permittivity film is the farthest low relative permittivity film from the silicon substrate, and wherein the seal ring extends continuously from the contact layer through the second low relative permittivity film.

2. The semiconductor device according to claim 1, further comprising: a plurality of the TSVs, wherein the seal ring surrounds the plurality of TSVs in a plan view.

3. The semiconductor device according to claim 1, wherein the seal ring has an octangular shape.

4. The semiconductor device according to claim 2, wherein the seal ring has an octangular shape in a plan view.

5. The semiconductor device according to claim 1, wherein the wiring layer connected to the semiconductor element through the contact layer is disposed outside of the seal ring.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other aspects, advantages and features will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which:

(2) FIG. 1 is a diagram showing a three-dimensional integrated circuit according to a first embodiment;

(3) FIG. 2 is a cross-sectional diagram showing the semiconductor device in the three-dimensional integrated circuit shown in FIG. 1;

(4) FIG. 3 is a diagram showing a positional relationship between a seal ring and a TVS in bird's eye view on a silicon substrate of a semiconductor device shown in FIG. 2;

(5) FIG. 4 is a diagram showing an example of a location and progress direction of a crack in the semiconductor device shown in FIG. 2;

(6) FIG. 5 is a diagram showing progress direction of a crack in bird's eye on the silicon substrate of the semiconductor device shown in FIG. 2;

(7) FIG. 6 is a cross-sectional diagram of a semiconductor device in a three-dimensional integrated circuit according to a second embodiment;

(8) FIG. 7 is a cross-sectional diagram of a semiconductor device in a three-dimensional integrated circuit according to a third embodiment;

(9) FIG. 8 is a diagram showing a positional relationship between a seal ring and a TVS in bird's eye view on a silicon substrate of the semiconductor device shown in FIG. 7;

(10) FIG. 9 is a cross-sectional diagram showing a semiconductor device according to a fourth embodiment;

(11) FIG. 10 is a part of a cross-sectional diagram of a semiconductor device according to a fifth embodiment;

(12) FIG. 11 is a part of a cross-sectional diagram of a semiconductor device according to a sixth embodiment; and

(13) FIG. 12 is a diagram showing an example of a known semiconductor device including a TSV.

DETAILED DESCRIPTION

(14) The following description and drawings are omitted and simplified as appropriate for clarity of explanation. Moreover, in the drawings, the same components are denoted by the same reference numerals, and repeated explanation is omitted as appropriate.

First Embodiment

(15) FIG. 1 shows a three-dimensional integrated circuit 80 according to a first embodiment. The three-dimensional integrated circuit 80 is composed of four semiconductor devices 100 that are laminated above a package substrate 90. The number of the semiconductor devices laminated above the package substrate 90 is four here, as an example, however this number is not limited to this and can be any value greater than or equal to two.

(16) FIG. 2 is a cross-sectional diagram the semiconductor device 100 of the three-dimensional integrated circuit 80. For easier comparison, the structure of a TSV in the semiconductor device 100 is made to be the same as that of the TSV in the semiconductor device 10 of the related art shown in FIG. 12. Moreover, for convenience of explanation, the direction extending from the silicon substrate 20 to the aluminum electrode 30, i.e., the direction extending upward from the bottom of the semiconductor device 100, shall be referred to as Y direction, and the direction vertical to the Y direction shall be referred to as X direction.

(17) In FIG. 2, the filled portions indicate a seal ring 110. As can be seen in FIG. 2, the seal ring 110 is provided, in the Y direction, from a low relative permittivity film 51 that is closest to the silicon substrate 20 (hereinafter referred to as a first low relative permittivity film) up to and through a low relative permittivity film 53 that is farthest from the silicon substrate 20 (hereinafter referred to as a second low relative permittivity film).

(18) FIG. 3 is a diagram showing a shape of the seal ring 110 and a positional relationship between the seal ring 110 and the TSV 60 in bird's eye view on the silicon substrate 20 from the aluminum electrode 30.

(19) Although not limited thereto, in this embodiment, the shape of the seal ring 110 is an octagon obtained by cutting four corners of a rectangle at 45 degrees in bird's eye view on the silicon substrate 20. The meaning of this shape is explained later.

(20) As shown in FIG. 3, the seal ring 110 is formed in the vicinity of the TSV 60 to surround the TSV electrode 61 with a gap from the outer periphery of the TSV 60 (the TSV electrode 61, to be more specific) in bird's eye view on the silicon substrate 20.

(21) FIG. 4 shows an example of a crack and progress direction of the crack that could be generated in the semiconductor device 100 shown in FIG. 2. In the layers of the semiconductor device, the portion closer to the connection to the TSV is more prone to cracks. In this example, the crack is generated in a region in the circled portion of the low relative permittivity film 52, and as indicated by the arrow in FIG. 4, the progress direction of the crack is the direction toward the outer periphery of the semiconductor device 100.

(22) FIG. 5 shows the progress direction of the crack in bird's eye view on the silicon substrate 20. The central black dot of FIG. 5 indicates the center of the TSV, and the arrows indicate the progress directions of the crack.

(23) A crack progresses from the center of the TSV radially toward the outer periphery of the semiconductor device. In this embodiment, the seal ring 110 inhibits progress of a crack, thereby suppressing damage of the low relative permittivity films.

(24) The seal ring 110 is also effective in supporting the films, hence the existence of the seal ring 110 can also suppress generation of a crack itself.

(25) Subsequently, the meaning of the shape of the seal ring 110 is explained. For example, assume that the one progress direction of a crack is a direction 1. In order to prevent a crack from progressing toward the direction 1, a blocking object having a shape substantially vertical to the direction 1 seems effective.

(26) As shown in FIG. 5, a crack progresses radially. The shape of the seal ring 110 to be a blocking object is made into an octagon by cutting four corners of a rectangle at 45 degrees, so that there are more directions substantially vertical to the seal ring 110 among the progression directions of a crack, which consequently improves blocking effect of a crack.

Second Embodiment

(27) A second embodiment also relates to a three-dimensional integrated circuit composed of a plurality of laminated semiconductor devices. FIG. 6 shows a semiconductor device 200 in the three-dimensional integrated circuit according to the second embodiment.

(28) The semiconductor device 200 has the same configuration as the semiconductor device 100 except for a seal ring 210 that is provided in place of the seal ring 110. Note that in FIG. 6, the seal ring 210 is also indicated by the filled portions.

(29) In the semiconductor device 100, the seal ring 110 is provided from the first low relative permittivity film 51 up to and through the second low relative permittivity film 53. On the other hand, as shown in FIG. 6, in the semiconductor device 200, the seal ring 210 extends upward to the topmost copper wiring layer (the fifth copper wiring layer LCU5 here) and extends downward to the contact layer LC.

(30) By providing the seal ring from the layer below the first low relative permittivity film 51 up to and through the layer above the second low relative permittivity film 53, it is possible to further improve the blocking effect from generation and progress of a crack in other layer not only in the low relative permittivity films.

(31) It is obvious that the upper limit of the seal ring is not limited to the top copper wiring layer as long as the coverage of the seal ring includes layers from the first low relative permittivity film 51 to the second low relative permittivity film 53, and may be any layer in or above the second low relative permittivity film 53 according to a wiring state of the semiconductor device 200. Similarly, as for the lower limit, it is not limited to the contact layer LC but may be any layer in or below the first low relative permittivity film 51 according to the wiring state of the semiconductor device 200.

Third Embodiment

(32) A third embodiment also relates to a three-dimensional integrated circuit composed of a plurality of laminated semiconductor devices. FIG. 7 shows a semiconductor device 300 in the three-dimensional integrated circuit according to the third enforcement. Only a difference from the semiconductor device 200 in FIG. 7 is explained.

(33) The semiconductor device 300 includes a plurality of TSVs (two TSVs in the example shown). As shown in FIG. 7, a TSV 360 is provided in addition to the TSV 60. The TSV 360 includes a TSV electrode 361 and a TSV electrode pad 362. The connection from the TSV electrode 361 to an aluminum electrode 330 is similar to the connection of the TSV 60 from the TSV electrode 61 to the aluminum electrode 30.

(34) Moreover, in the semiconductor device 300, a seal ring 310 is provided in place of the seal ring 210 in the semiconductor device 200. Note that also in FIG. 7, the seal ring 310 is indicated by the filled portions.

(35) In a similar manner to the seal ring 210, the seal ring 310 is provided, in the Y direction from the contact layer LC up to and through the fifth copper wiring layer LCU5.

(36) FIG. 8 is a diagram showing a positional relationship between the TSV 60, the TSV 360, and the seal ring 310 in bird's eye view on the silicon substrate 20 from the wafer front surface.

(37) As shown in FIG. 8, the seal ring 310 is formed in the vicinity of the TSV 60 (the TSV electrode 61, to be more specific) and the TSV 360 (the TSV electrode 361, to be specific) to surround the TSV electrode 61 and the TSV electrode 361. The shape of the seal ring 310 is an octagon in a similar manner to the seal ring 110 and the seal ring 210.

(38) As described above, the seal ring is formed to surround the plurality of TSVs in bird's eye view on the silicon substrate, thereby suppressing generation and progress of a crack in the insulating films and also reducing the number of seal rings more than in the case of providing a seal ring for each TSV, which is advantageous for the layout of the semiconductor device.

(39) Note that FIG. 7 shows an example in which the number of the TSVs included in the semiconductor device is two, and one seal ring is provided for the two TSVs. For example, when the number of TSVs is three or greater, these TSVs may be divided into a plurality of groups according to spaces between the TSVs and a wiring state of a semiconductor device, and the seal ring may be provided for each group.

(40) It is obvious that the seal ring 310 may also be provided in any layer as long as the lower limit is in or below the first low relative permittivity film 51 and the upper limit is in or above the second low relative permittivity film 53 in the Y direction.

Fourth Embodiment

(41) The semiconductor devices according to the above embodiments are examples in which the TSVs are connected to the aluminum electrodes. This technique can be applied to a semiconductor device in which a TSV is not connected to an aluminum electrode. The fourth embodiment is related to such a semiconductor device.

(42) FIG. 9 shows a semiconductor device 400 in a three-dimensional integrated circuit according to the fourth embodiment. This semiconductor device 400 is a semiconductor device of the topmost layer of the three-dimensional integrated circuit, for example.

(43) As shown in FIG. 9, in the semiconductor device 400, the TSV 60 is connected through to the fifth copper wiring layer LCU5. Moreover, the fifth copper wiring layer LCU5 is connected to the semiconductor element 40 via the fourth via layer LV4, the third copper wiring layer LCU3, the third via layer LV3, the second copper wiring layer LCU2, the second via layer LV2, the first copper wiring layer LCU1, and the contact layer LC.

(44) The seal ring 410 indicated by the filled portions is provided from the contact layer LC up to and through the copper wiring layer (the fourth copper wiring layer LCU4) that is one layer below the fifth copper wiring layer LCU5.

(45) By doing so, the seal ring 410 will not interfere wiring from the fifth copper wiring layer LCU5 to the semiconductor element 40 and can prevent generation and/or progress of a crack in the low relative permittivity films.

(46) Note that in the semiconductor device 400, the seal ring 410 is provided down to and through the contact layer LC in the downward direction, however the seal ring 410 may not be provided in the contact layer LC but may be provided up to and through the first low relative permittivity film 51. It is obvious that in the upward direction, the seal ring 410 may not be provided up to and through the fourth copper wiring layer LCU4 and may be provided down to and through the second low relative permittivity film 53.

Fifth Embodiment

(47) As explained above, the seal ring is provided from the low relative permittivity film that is closest to the silicon substrate (the first low relative permittivity film) up to and through the low relative permittivity film that is farthest from the silicon substrate (the second low relative permittivity film) thereby to suppress generation and/or progress of a crack in the low relative permittivity films. The seal ring is provided down to and through the contact layer that is below the first low relative permittivity film, i.e., down to the front surface of the diffusion layer, and connected to the diffusion layer, so that the seal ring can have the same potential as the substrate. Therefore, the seal ring can be used for power supply to nearby semiconductor elements. One example is explained with reference to FIG. 9.

(48) FIG. 10 is a cross-sectional diagram of a semiconductor device 500 in a three-dimensional integrated circuit according to a fifth embodiment. In FIG. 10, only up to the second copper wiring layer LCU2 is shown and layers above the second copper wiring layer LCU2 are not shown.

(49) In the semiconductor device 500, the seal ring 510 indicated by the filled portions is provided down to and through the diffusion layer LD.

(50) The semiconductor element 40 is an N-type transistor, and the diffusion layer LD is a P+ diffusion layer, for example. The drain electrode and the source electrode (GND) of the semiconductor element 40 are provided in the first copper wiring layer LCU1, and supply power to the drain terminal and the source terminal of the semiconductor element 40, respectively, via the contact layer LC.

(51) In this case, in the first copper wiring layer LCU1, the seal ring 510 is connected to the drain electrode of the semiconductor element 40 by connection wiring to enable power supply to the source terminal of the semiconductor element 40.

Sixth Embodiment

(52) A semiconductor device 600 according to a sixth embodiment shown in FIG. 11 is also an example in which a seal ring is provided down to and through the diffusion layer and power is supplied to a semiconductor element. Also in the semiconductor device 600, as an example, the semiconductor element 40 is an N-type transistor, and the diffusion layer LD is a P+ diffusion layer.

(53) The TSV 60 is connected to an external GND not shown via the TSV electrode pad 62. In this case, as shown in FIG. 11, in the first copper wiring layer LCU1, a seal ring 610 is connected to the drain electrode of the semiconductor element 40 and the TSV electrode 61 of the TSV 60 by connection wiring to enable power supply to the source terminal of the semiconductor element 40.

(54) While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.

(55) Further, the embodiments described above can be combined as desirable by one of ordinary skill in the art and the scope of the claims is not limited by these embodiments.

(56) Furthermore, it is noted that, Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.