Integrated circuit assembly

Abstract

An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.

Claims

1. An integrated circuit (IC) die comprising: a top surface and a bottom surface; and a plurality of spaced apart ground connection traces positioned between said top surface and said bottom surface; wherein a hole in said die exposes said plurality of spaced apart ground connection traces.

2. The IC die of claim 1 further comprising conductive filler filling said hole and electrically connecting said plurality of ground connection traces.

3. The IC die of claim 2 wherein said hole extends through said top surface and said bottom surface.

4. An integrated circuit (IC) package comprising an IC die having a top surface and a bottom surface and a plurality of spaced apart ground connection traces positioned between said top and bottom surfaces; wherein a hole in said IC die exposes said ground connection traces.

5. The IC package of claim 4 further comprising conductive filler filling said hole and electrically connecting said ground connection traces.

6. The IC package of claim 4 wherein said hole in said IC die extends through said top surface and said bottom surface of said IC die.

7. The IC package of claim 5 wherein said IC die is mounted on a die attach pad (DAP) with said conductive filler in said hole electrically connected to said DAP.

8. A method of making an integrated circuit (IC) assembly comprising: exposing ground connection traces in an IC die by making a hole in the die that intersects the ground connection traces.

9. The method of claim 8 further comprising filling the hole with conductive filler.

10. The method of claim 9 further comprising attaching the die to a leadframe die attach pad (DAP) such that the conductive filler is electrically connected to the DAP.

11. The method of claim 8 wherein said exposing ground connection traces comprises extending the hole between top and bottom surfaces of the IC die.

12. The method of claim 10 further comprising wire bonding contact surfaces on a top surface of the die with leads of the leadframe and not the DAP.

13. The method of claim 12 further comprising encapsulating the die and leadframe in mold compound.

14. The method of claim 13 further comprising plating exposed surface portions of the leads.

15. The method of claim 12 further comprising singulating the encapsulated leadframe from adjacent encapsulated leadframes.

16. An integrated circuit (IC) package comprising: an IC die having a first surface and a second surface and a conductive material extending from the first surface to the second surface, the conductive material connected to a plurality of ground connection traces in the IC die; and a lead frame including a die attach pad and a set of leads, the die attach pad electrically connected to the conductive material.

17. The IC package of claim 16 further comprising a mold compound encapsulating portions of the IC die and the lead frame.

18. The IC package of claim 16, wherein the conductive material occupies a hole that extends from the first surface to the second surface, and wherein the hole includes a cylindrical shape.

19. The IC package of claim 16, wherein the plurality of ground connection traces are arranged in parallel and spaced apart relationship with each other.

20. The IC package of claim 16, wherein the conductive material includes silver epoxy.

Description

BRIEF DESCRIPTION OF THE DRAWING

(1) FIG. 1 is a top plan view of a prior art die and lead frame assembly.

(2) FIG. 2 is a top plan view of a die and lead frame assembly.

(3) FIG. 3 is a top plan view of a die wafer at an initial stage of a new die fabrication process disclosed herein.

(4) FIG. 4 is a top plan view of a die wafer mounted on a wafer ring at another stage of the new die fabrication process disclosed herein.

(5) FIG. 5 is a top plan view of the die wafer and wafer ring of FIG. 4, in which each die portion has a central hole formed therein.

(6) FIG. 6 is a top plan view of the die wafer and wafer ring of FIG. 5, after wafer singulation/dicing.

(7) FIG. 7 is a top plan view of a lead frame with one of the singulated dies of FIG. 6 mounted on a die attachment pad of the lead frame.

(8) FIG. 8 is a magnified isometric view of a portion of the die of FIG. 7 in which a hole is drilled.

(9) FIG. 9 is the magnified view of FIG. 8 after the hole has been filled with conductive material.

(10) FIG. 10 is a cross-sectional view of the die and leadframe of FIG. 6.

(11) FIG. 11 is a flow diagram of a method of making an integrated circuit assembly.

(12) FIG. 12 is a flow diagram of a method of eliminating wire sweep between ground and signal wires in an integrated circuit package.

DETAILED DESCRIPTION

(13) FIG. 1 is a top plan view of a prior art die and lead frame assembly. A lead frame 10 has a die attachment pad (DAP) 12 and a plurality of leads 14. A die 16 is mounted on the DAP 12. The die 16 has a top surface 18, which includes a plurality of die electrical contact surfaces 22. A first plurality of bond wires 30 are ball bonded to die contact surfaces 22 at first ends thereof and are stitch bonded to leads 14 at the second ends thereof. A second plurality of bond wires 32 are ball bonded to certain die contact surfaces 23 that are connected with ground traces within the die 16. The opposite ends of these wires 32 are stitch bonded to the DAP 12.

(14) Wire sweep refers to an IC package manufacturing problem that occurs when bond wires are not properly aligned in the horizontal plane. Wire sweep can occur during the wire bonding process, during handling after wire bonding, or during molding. Wire sweep can affect electrical performance by changing the mutual inductance of adjacent wires and SSN (simultaneous switching noise). If the wires touch, they will short. Another problem associated with wire bonding is that the stitch bonds formed on a die attach pad (DAP) can cause a die mounted on the DAP to delaminate from it.

(15) Applicants have developed a die that eliminates the need for bond wires electrically connected to the ground traces. A die/leadframe assembly including such a die 66 mounted on a DAP 62 of a leadframe 60 is illustrated in FIG. 2. Bond wires 80 connect die contact surfaces 72, which are not connected to ground traces, to leads 64. These bond wires 80 are connected only to the leadframe leads 64, not the DAP 62. The ground traces in the die are electrically connected to the DAP 62 through conductive filler material 68 filling a hole 69 extending through the die 66. The conductive material 68 is exposed at the bottom of the die 66. Ground traces (not shown in FIG. 2) within the die 66 electrically contact the conductive filler material 68.

(16) A die 116, which may be similar or identical to die 66, and a method by which this die 116 is produced and mounted on a leadframe are described in detail with reference to FIGS. 3-9 below. The elimination of bond wires connecting ground traces in a die to a DAP reduces the risk of wire sweep. This reduction in bond wires connected to a DAP effectively increases the space between the remaining bond wires. Removal of bond wires attached to the DAP obviates wire stitching on the DAP, and the problem of die/DAP delamination caused by wire stitching.

(17) FIG. 3 is a top plan view of a die wafer 100 after wafer fabrication.

(18) FIG. 4 is a top plan view of the die wafer 100 of FIG. 1 mounted on a conventional wafer ring 102 for processing.

(19) FIG. 5 is a top plan view of the die wafer 100 and wafer ring 102 of FIG. 4, in which each wafer portion that will ultimately become a die has a central hole 104 formed therein. Such holes 104 may be conventionally created by mechanical or laser drilling. The holes 104, in one example embodiment, extend through the entire thickness of the wafer 100.

(20) FIG. 6 is a top plan view of the die wafer 100 and wafer ring 102 of FIG. 5 after dicing (singulation). During singulation, the wafer 100 is singulated along saw streets 106 to separate the wafer into a plurality of individual dies 116, each having a hole 104 extending through it.

(21) FIG. 7 is a top plan view of a lead frame 110 with one of the singulated dies 116 of FIG. 6 mounted on a die attachment pad (DAP) 112 of the lead frame 110. The leadframe 110 has a plurality of leads 114 positioned around the DAP 112.

(22) FIG. 8 is a magnified isometric view of a portion of the die 116 of FIG. 7 containing a central hole 104. The hole 104 exposes a plurality of planar ground traces 122, 124, 126, and 128, which are arranged in parallel, spaced apart, stacked relationship within the die substrate.

(23) FIG. 9 is the magnified view of FIG. 8 after the hole 104 has been filled with a conductive material 130, such as silver epoxy or other conductive filler material.

(24) FIG. 10 is a cross sectional view of the die 116 and DAP 112 of FIG. 7, in which the hole 104 in the die 116 has been filled with conductive filler material 130. The filler material 130 electrically connects the ground traces 122, 124, 126, and 128. The filler material may be directly connected to the DAP 112 or it may be connected to the DAP by a layer of other conductive attachment material 132, such as conductive adhesive, solder or other conductive attachment material. In this embodiment the hole 104 extends entirely through the die 104, i.e., it extends through the top surface 117 and bottom surface 118 of the die. In other embodiments (not shown) the hole 104 and filler 130 extends up from the bottom surface 118 of the die sufficiently far to expose and connect all of the conductive traces 122, 124, 126, 128, but does not extend to the top surface 117 of the die. Bond wires 142, 144 have first ends thereof connected, as by ball bonds 141, 143, to electrical contact surfaces provided on the top surface 117 of the die 116 and have second ends thereof connected, as by stitch bonds 145, 147 to leads 114. There are no bond wires attached to the DAP 112.

(25) As previously discussed, FIG. 2 is a top plan view of a die 66 that may be identical to die 116, which is attached to a leadframe 60 that may be identical to leadframe 110.

(26) FIG. 10 is a flow diagram of a method of making an integrated circuit assembly. The method includes, as shown at block 301, exposing ground connection traces in an IC die by making a hole in the die that intersects the ground connection traces.

(27) FIG. 11 is a flow diagram of a method of eliminating wire sweep between ground and signal wires in an integrated circuit package. The method comprises, as shown at block 401, providing a plurality of stacked ground connection traces in the die; and, as shown at block 402, forming a hole through the die to expose the ground connection traces.

(28) Expressly disclosed in detail herein are embodiments of an integrated circuit (IC) die that includes a plurality of spaced apart ground connection traces positioned between a top surface and bottom surface of the die with a hole in the die that exposes the plurality of spaced apart ground connection traces. Methods of making such a die and various uses thereof in combination with a leadframe have also been expressly disclosed herein. Various alternative embodiments of this integrated circuit die and methods of making and using it may become obvious to those skilled in the art after reading this disclosure. It is intended that the appended claims be construed broadly to cover such alternative embodiments, except as limited by the prior art.