GaN-on-Si SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GaN TRANSISTORS AND METHODS OF FABRICATION THEREOF

Abstract

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

Claims

1. A wafer scale nitride semiconductor device structure comprising: a silicon substrate having formed thereon an GaN epi-layer stack for a plurality of GaN die (GaN-on-Si die), said plurality of GaN die being arranged as an array with dicing streets therebetween; each GaN die comprising: a part of the GaN epi-layer stack, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two dimensional electron gas (2DEG) active layer for the lateral GaN transistor; a conductive metallization layer formed thereon defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective source and drain electrodes of the lateral GaN transistor; said source, drain and gate electrodes being provided on a front-side of the epi-layer stack over an active area of the die, an inactive area of the GaN epi-layer stack surrounding said active area of each die, and an overlying interconnect structure comprising metallization and dielectric layers formed thereon; and a trench structure formed around the periphery of each GaN die in said inactive area, the trench structure comprising a trench etched through any overlying layers of the interconnect structure, through the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below the interface between the silicon substrate and the GaN epi-layer stack.

2. The device structure of claim 1, wherein the trench structure is laterally spaced from the dicing street.

3. The device structure of claim 1, wherein the trench structure is laterally spaced from a scribe line of the dicing street.

4. The device structure of claim 1, wherein the trench structure extends across the dicing street between adjacent die.

5. The device structure of claim 1, wherein the trench structure further comprising a trench cladding, the trench cladding comprising at least one passivation layer extending over the inner sidewalls of the trench and sealing exposed surfaces of any overlying layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate.

6. The device structure of claim 1, further comprising at least one overlying passivation layer, the at least one overlying passivation layer extending conformally over surfaces of the die and extending into the trench to form a trench cladding, the trench cladding extending over the inner sidewalls of the trench and sealing exposed surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate.

7. The device structure of claim 1, wherein the trench structure further comprising a trench cladding, the trench cladding comprising a metal layer and an overlying passivation layer, the trench cladding extending over the inner sidewalls of the trench and sealing exposed surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate.

8. The device of claim 7, wherein the metal layer of the trench cladding is conductive and connects the silicon substrate to the source of the transistor.

9. The device of claim 7, wherein the die further comprises a seal ring formed over the inactive region of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure being formed between the sealing ring and the dicing street, and wherein the conductive metal layer of the trench cladding connects the silicon substrate to a metallization layer of the seal ring.

10. The device of claim 1, wherein the die further comprises a seal ring formed over the inactive region of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure is formed in the inactive region between the seal ring and the dicing street.

11. A nitride semiconductor device comprising: a GaN die comprising: a silicon substrate and a GaN epi-layer stack formed thereon comprising a GaN/AlGaN hetero-layer structure defining a two dimensional electron gas (2DEG) active layer for a lateral GaN transistor; a conductive metallization layer formed thereon defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective source and drain electrodes of the lateral GaN transistor; said source, drain and gate electrodes being provided on a front-side of the epi-layer stack over an active area of the die, an inactive area of the GaN epi-layer stack surrounding said active area of each die; and an overlying interconnect structure comprising metallization and dielectric layers formed thereon; a trench structure formed around the periphery (all sides) of the GaN die extending through any layers of the overlying interconnect structure, through layers of the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below the interface between the silicon substrate and the epi-layer stack.

12. The device of claim 11, wherein the trench structure is laterally spaced from the diced edge of the die.

13. The device of claim 11, wherein the trench structure extends to the edge of the die.

14. The device structure of claim 11, wherein the trench structure further comprising a trench cladding, the trench cladding comprising at least one passivation layer extending over the inner sidewalls of the trench and sealing exposed surfaces of any overlying layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate.

15. The device structure of claim 11, further comprising at least one overlying passivation layer, the at least one overlying passivation layer extending conformally over surfaces of the die and extending into the trench to form a trench cladding, the trench cladding extending over the inner (proximal) sidewalls of the trench and sealing exposed surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate.

16. The device structure of claim 11, wherein the pre-dicing trench structure further comprises a trench cladding, the trench cladding comprising a metal layer and an overlying passivation layer, the trench cladding extending over the inner (proximal) sidewalls of the trench and sealing exposed surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate.

17. The device of claim 16, wherein the metal layer of the trench lining is conductive and connects the silicon substrate to the source of the transistor.

18. The device of claim 16, wherein the die further comprises a seal ring formed over the inactive region of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure being formed between the sealing ring and the dicing street, and wherein the conductive metal layer of the trench lining connects the silicon substrate to a metallization layer of the seal ring.

19. The device of claim 11, wherein the die further comprises a seal ring formed over the inactive region of the GaN epi-layer stack and surrounding the lateral GaN transistor, and the trench structure is formed in the inactive region between the sealing ring and the die edges.

20. The device structure of claim 11, wherein the lateral GaN transistor comprises a plurality of transistor islands of a multi-island transistor, and further comprising a plurality of trenches dividing the active device area of the transistor into a plurality of areas, each of said plurality of areas accommodating a plurality of transistor islands.

21. The device structure of claim 11, wherein the lateral GaN transistor comprises a plurality of transistor islands of a multi-island transistor, and further comprising a plurality of trenches dividing the active device area of the transistor into a plurality of areas, each of said plurality of areas accommodating an individual transistor island.

22. A method of fabrication of a nitride semiconductor device structure as defined in claim 11, comprising steps of: providing a silicon substrate having formed thereon a GaN epi-layer structure for a plurality of GaN die, the GaN die being arranged as an array with dicing streets therebetween; each GaN die comprising: a part of the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two dimensional electron gas (2DEG) active layer for the lateral GaN transistor; a conductive metallization layer formed thereon defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective source and drain electrodes of the lateral GaN transistor; said source, drain and gate electrodes being provided on a front-side of the epi-layer stack over an active area of the die, an inactive area of the GaN epi-layer stack surrounding said active area of each die; and an overlying interconnect structure comprising metallization and dielectric layers formed thereon; and etching a trench structure around all sides of each GaN die, extending through any layers of the overlying interconnect structure, through layers of the GaN epi-layer stack and into a surface region of the silicon substrate to a depth below the interface of the GaN epi-layer stack and the silicon substrate, the trench structure being laterally spaced from a dicing street of each die edge.

23. The method of claim 22, further comprising providing a trench cladding comprising at least one dielectric passivation layer, and a optionally conductive metal layer underlying said at least one dielectric passivation layer, the trench cladding extending over the inner sidewall of the trench and sealing exposed surfaces of the interconnect structure, the layers the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate.

24. The method of claim 22, wherein defining a trench structure comprises: masking at least active areas of each GaN die and part of a surrounding inactive region; performing a sequence of dry etching steps comprising: removing layers within the trench extending over the GaN epi-layers, removing the GaN epi-layers within the trench, and removing a surface region of the silicon substrate within the trench to a depth below the interface of the GaN epi-layers and the silicon substrate.

25. The method of claim 22, further comprising dicing the wafer along scribe lines laterally spaced from each trench.

26. The method of claim 22, wherein dicing comprises any one of sawing, laser ablation, plasma dicing, stealth dicing, laser induced splitting/cleaving, and a combination thereof

27. The method of claim 23, wherein providing a metal layer of the trench lining comprises providing a metal barrier layer against electro-migration of contaminant ions.

28. The method of claim 23, wherein the conductive metal layer of the trench lining connects the silicon substrate to the source of the GaN transistor.

29. The method of claim 23, wherein each die further comprises a seal ring, and the conductive metal layer of the trench lining connects the silicon substrate to a metallization layer of the seal ring.

30. The method of claim 22, wherein, when the lateral GaN transistor comprises a large area multi-island lateral GaN transistor, and further comprising etching a plurality of trenches dividing GaN epi-layers of each die area into a plurality of areas, each of said plurality of areas accommodating a plurality of transistor islands.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In the drawings, identical or corresponding elements in the different Figures have the same reference numeral, or corresponding elements have reference numerals incremented by 100 in successive Figures.

[0062] FIG. 1 (Prior Art) shows a simplified schematic diagram of a plan view of part of a silicon wafer comprising a plurality of GaN-on-Si die with dicing streets for dicing of the wafer along lines x-x and y-y;

[0063] FIG. 2 (Prior Art) shows a simplified schematic cross-sectional diagram of part of a GaN-on-Si die comprising a lateral GaN power transistor comprising a GaN/AlGaN heterostructure;

[0064] FIG. 3 (Prior Art) shows a simplified schematic cross-sectional diagram of part of a GaN-on-Si wafer comprising a die., and parts of neighbouring die, e.g. through line A-A of die.sub.n in FIG. 1, wherein each die comprises a lateral GaN power transistor comprising a GaN/AlGaN heterostructure, to illustrate schematically dicing induced defects and crack propagation, such as may be caused by conventional wafer sawing;

[0065] FIG. 4 (Prior Art) shows a simplified schematic cross-sectional diagram of part of a GaN-on-Si wafer comprising a die.sub.n, and parts of neighbouring die, e.g. through line A-A of die.sub.n in FIG. 1, wherein each die comprises a lateral GaN power transistor comprising a GaN/AlGaN heterostructure and a surrounding seal ring, to illustrate schematically dicing induced defects and crack propagation, such as may be caused by conventional wafer sawing;

[0066] FIG. 5 shows a simplified schematic diagram of a plan view part of a silicon wafer comprising a plurality of GaN-on-Si die with dicing streets for dicing of the wafer along lines x-x and y-y, and further comprising a pre-dicing trench according to an embodiment of the present invention;

[0067] FIG. 6 shows a simplified schematic cross-sectional diagram of part of a GaN-on-Si wafer comprising a die.sub.n, and parts of neighbouring die, wherein each die comprises a lateral GaN power transistor comprising a GaN/AlGaN heterostructure and a pre-dicing trench formed around the periphery of the die, according to a first embodiment of the present invention;

[0068] FIG. 7 shows a simplified schematic cross-sectional diagram of part of a GaN-on-Si wafer comprising a die.sub.n, and parts of neighbouring die, wherein each die comprises a lateral GaN power transistor comprising a GaN/AlGaN heterostructure, a pre-dicing trench formed around the periphery of the die and a protective edge sealing layer formed on inner (proximal) sidewalls of the pre-dicing trench, according to a second embodiment of the present invention;

[0069] FIG. 8 shows a simplified schematic cross-sectional diagram of part of a GaN-on-Si wafer comprising a die., and parts of neighbouring die, wherein each die comprises a lateral GaN power transistor comprising a GaN/AlGaN heterostructure and pre-dicing trench formed around the periphery of the die, and a protective edge sealing layer formed conformally over the active region of the die and extending over the inner (proximal) sidewalls of the pre-dicing trench, according to a third embodiment of the present invention;

[0070] FIGS. 9 to 13 shows a series of simplified schematic cross-sectional diagrams through part of a GaN-on-Si wafer to illustrate a process flow for fabrication of a GaN device structure comprising a lateral GaN power transistor comprising a GaN/AlGaN heterostructure with a surrounding seal ring, and pre-dicing trench, according to fourth embodiment of the present invention;

[0071] FIG. 14 shows a simplified schematic cross-sectional diagram of part of a GaN-on-Si wafer comprising a lateral GaN transistor, according to another embodiment of the present invention; and

[0072] FIG. 15 shows a simplified schematic cross-sectional diagram of part of a GaN-on-Si wafer comprising a lateral GaN transistor according to yet another embodiment of the present invention.

[0073] The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, of preferred embodiments of the invention, which description is by way of example only.

DETAILED DESCRIPTION OF EMBODIMENTS

[0074] FIG. 1 (Prior Art) shows a simplified schematic diagram of a plan view of part of a GaN-on-silicon wafer 1 comprising a silicon substrate 2 on which is defined a plurality of GaN-on-Si die 10, each comprising a GaN semiconductor device such as a GaN HEMT. The GaN-on Si-die 10 are arranged as an array, with dicing streets 8 in between each die, for die singulation by dicing of the wafer along scribe lines 16, i.e. lines in directions x-x and y-y, between adjacent die. Each die 10 comprises an active device area 4, i.e. the hetero-layer structure defining the 2DEG region on which the source, drain and gate electrodes of the GaN HEMT are formed, surrounded by an inactive area 6 which separates the active area from edges of the die 17. Optionally, a protective structure, such as a seal ring 14, may be provided around the die, in the inactive area 6, near the die edge 17. By way of example, a GaN semiconductor device structure 100, comprising a lateral GaN power transistor, is illustrated in a simplified schematic cross-sectional view shown in FIG. 2. The GaN transistor is fabricated on a silicon substrate 102. The GaN semiconductor layers 112 comprise one or more buffer layers or intermediate layers 104, a GaN layer 106, and an overlying AlGaN layer 108, which are formed epitaxially on the native silicon substrate 102. The latter may be referred to as the growth substrate. The GaN/AlGaN heterostructure layers 106/108 create a 2DEG active region 110 in device regions of the GaN-on-Si substrate. The stack of GaN epitaxial layers that is formed on the silicon substrate, i.e. intermediate layers 104, GaN layer 106, and AlGaN layer 108, and any intervening layers not actually illustrated, will be referred to below as the epi-layer stack or epi-stack 112. After formation of the epi-stack 112, source, drain and gate electrodes are formed. For example, a conductive metal layer, e.g. a layer of aluminum/titanium (Al/Ti) which forms an ohmic contact with the underlying GaN heterostructure layer, is deposited to define a source electrode 120 and a drain electrode 122. A gate electrode 126, is also defined over the channel region between the source and drain electrodes, e.g. a gate electrode comprising a Schottky metal such as palladium (Pd). This device structure can be fabricated as a depletion mode (D-mode) device which is normally on, or as an enhancement mode (E-mode) device, which is normally off. For example, for a D-mode HEMT, the GaN heterostructure may comprises a layer of undoped GaN and a layer of undoped AlGaN, with the gate electrode formed on the AlGaN layer; and for an enhancement mode (E-mode) HEMT, the GaN hetero-structure would further include a p-type layer provided in the region under the gate electrode, e.g. p-type GaN or p-type AlGaN under the gate. Alternatively, a similar epi-layer stack comprising a GaN/AlGaN heterostructure, with anode and cathode electrodes provided thereon, may be used to form a high voltage/high current diode.

[0075] For simplicity, in the GaN transistor structure illustrated in FIG. 1, only a single source electrode, drain electrode and gate electrode is illustrated, and overlying interconnect layers, i.e. one or more metallization layers and intervening dielectric layers, are not shown.

[0076] For more details of device structures, layout topologies and methods of fabrication of large area, high voltage/high current lateral GaN transistors, reference is made, for example, to U.S. Pat. No. 9,153,509 to Klowak et al. entitled Fault Tolerant Design for Large Area Nitride Semiconductor Devices, issued Oct. 6, 2015 to GaN Systems Inc., and related references cited therein, having common ownership with this application. These references are incorporated herein by reference in their entirety.

[0077] FIG. 3 (Prior Art) shows a simplified schematic cross-sectional diagram of part of the GaN-on-Si wafer 1 shown in FIG. 2, i.e. a cross-section through line A-A of FIG. 1, showing die, 10 and parts of neighbouring die. Each die 10 comprises a lateral GaN power transistor 214 formed on a silicon substrate 202. The GaN transistor structure 214 comprises a plurality of GaN epitaxial layers, i.e. GaN epi-layer stack 212. The GaN epi-layer stack 212 includes a GaN/AlGaN heterostructure providing a 2DEG active region 210. Source electrode S, drain electrode D and gate electrode G of the lateral GaN transistor are formed on the 2DEG active region 210. Also shown are overlying Back End of the Line (BEOL) layers 230, i.e. comprising first and second metallization layers 232 (M1) and 234 (M2), and intervening dielectric layers 236 and 238. Conductive vias 240 interconnect the source and drain electrodes (S, D) to respective overlying metallization layers M1 and M2, and M2 provides external source and drain contact pads 242, 244. For simplicity, similar to FIG. 2, only a single source electrode S and drain electrode D are shown, and the interconnections from the gate electrode G to an external gate contact pad are not illustrated.

[0078] Although only one transistor element is illustrated for die 10 in the simplified schematics in FIG. 3, it will be appreciated that large area, multi-island lateral GaN HEMTs may be provided, e.g. as disclosed in the above mentioned U.S. Pat. No. 9,153,509 As is conventional, many GaN-on-Si die are patterned on a single, large area silicon substrate wafer and the wafer is then diced to provide separate individual GaN-on-Si die, as illustrated schematically in FIG. 2.

[0079] As shown schematically in FIG. 3, the die area 201 comprises an active area of the device 204 surrounded by an inactive area 206. The latter extends into dicing streets 208 along each of the four sides of the die 10. During die singulation, the wafer is diced along scribe lines 216, e.g. using conventional sawing or laser grooving, a combination thereof, to cut through all layers of the wafer as indicated by line 250, representing the kerf of a saw blade or laser groove. Thus, when die are separated as indicated at 260, the diced edges 217 of the die expose edges of the BEOL layers and expose edges of the plurality of layers forming the GaN epi-layer stack. As mentioned above, interlayer stresses due to lattice mismatch of the GaN epi-layers and the silicon substrate can cause propagation of dicing induced defects and cracking of both the epi-layer stack and the BEOL dielectric layers, i.e. causing cracks 282 in the epi-layers 212 and cracks 284 in the dielectric layers 236 and 238. If these dicing induced defects and cracks are not detected during device testing, these defects and/or cracks can potentially migrate into active regions of the device, and the reliability of the device is then compromised.

[0080] Optionally, the die 10 further comprises a seal ring 280 extending around the periphery of the die, as illustrated schematically in FIG. 4. Many elements of FIG. 4 are similar to those of FIG. 3 and are labelled with the same part numbers. The seal ring 280 comprises part of the BEOL layers and is formed over the inactive device area 206 which surrounds the active device area 204. The seal ring structure 280 helps to reduce crack propagating into active areas of the device interconnect layers, and also helps to block electro-migration of contaminant ions. However, as illustrated, the diced edges 217 of the epi-layer stack are exposed after wafer singulation. As described with respect to the structure shown in FIG. 3, any dicing induced defects and cracks 282 can potentially migrate into active regions of the transistor, leading to reliability issues.

[0081] In FIGS. 2 to 4, the thicknesses and other dimensions of the layers are not shown to scale. Typically the GaN epi-layer stack has a thickness of about 2 m to 6 m, while the silicon substrate may have a thickness of 200 m to 500 m or more. The silicon substrate may be thinned somewhat during wafer post-processing after fabrication of the semiconductor layers is completed. For a large area high voltage/high current lateral GaN transistor, the die size may be in the range from 10 mm.sup.2 to 100 mm.sup.2, e.g. about 2 mm6 mm or 10 mm10 mm. The dicing streets between the die may be 60 m to 120 m wide, for example. An inactive region, e.g. having a width of in a range from about 25 m to about 80 m, typically extends around the active 2DEG region of the transistor, to separate the active region of the transistor from the diced edges of the die. Where a seal ring 280 is provided, as illustrated in FIG. 4, it may similarly have a width in a range from about 20 m to 30 m, and provides further lateral separation between the die edge and the active region of the lateral GaN transistor. Typically the seal ring would be spaced about 20 m to 30 m from the die edge, and spaced at least 5 m, and perhaps 20 m to 30 m, from the active region.

[0082] FIG. 5 shows a simplified schematic diagram of part of a GaN-on-silicon wafer 400 according to an embodiment of the present invention, comprising a silicon substrate 302 on which is defined a plurality of GaN-on-Si die 110, arranged as an array, with dicing streets 308 in between each die, for die singulation by dicing of the wafer along scribe lines 316, i.e. lines in directions x-x and y-y, between adjacent die. Each die 110 comprises an active device area 304 surrounded by an inactive area 306. Optionally, a protective structure such as a seal ring 380 may be provided around the die in inactive area 306, near the die edge 317.

[0083] A pre-dicing trench 388 is formed around the periphery of the chip, i.e. around all edges of the die, on the inactive area adjacent to, or close, to the die edge. As illustrated schematically, the trench lies between the seal ring 380 and the die edge 317.

[0084] FIG. 6 shows a simplified schematic cross-sectional diagram of part of the GaN-on-Si wafer 600 according to a first embodiment, e.g. a cross section through A-A of FIG. 5 showing die. 110 and parts of neighbouring die.

[0085] Many elements of FIG. 6 are similar to those of FIG. 3 and are labelled with the same part numbers incremented by 100. That is, each die 110 comprises a lateral GaN power transistor 314 formed on a silicon substrate 202. The GaN transistor structure 314 comprises a plurality of GaN epitaxial layers, i.e. GaN epi-layer stack 312. The GaN epi-layer stack 312 includes a GaN/AlGaN heterostructure providing a 2DEG active region 310. Source electrode S, drain electrode D and gate electrode G of the lateral GaN transistor are formed on the 2DEG active region 310. Also shown are overlying Back End of the Line (BEOL) layers 330, i.e. comprising first and second metallization layers 332 (M1) and 334 (M2), and intervening dielectric layers 336 and 338. Conductive vias 340 interconnect the source and drain electrodes (S, D) to respective overlying metallization layers M1 and M2, and M2 provides external source and drain contact pads 342, 344.

[0086] The device structure of this embodiment further comprises a trench 388 etched around the periphery of each die area 301. The trenches 388 extend into the silicon substrate and are formed prior to wafer dicing. These trenches will be referred to as pre-dicing trenches. The trenches separate the active area of each die, and part of the surrounding inactive area, from the dicing street. For example, the trenches 388 have a width in the range of about 15 m to 20 m, to provide an aspect ratio of 3:1 or 4:1. Thus, as illustrated schematically in FIG. 6, after dicing, any dicing induced defects or cracks 382, 384 are blocked by the trench from propagation or migration into the active area 304 of the device structure.

[0087] As illustrated in FIG. 7, a device structure according to a second embodiment is similar to that shown in FIG. 7. Additionally, in a device structure of this embodiment, a trench cladding 390 (trench lining) comprising an edge sealing layer or protective layer, is provided on at least the inner or proximal side walls of the pre-dicing trenches, surrounding each die. The trench cladding 390 may comprise one or more conformal dielectric layers, and optionally a metal layer, provided on the inner (proximal) sidewalls 392 of the trench, which seal any exposed edges of the epi-layer stack and overlying BEOL layers. In referring to inner sidewalls 392 of the trench 388, this means the sidewalls which are proximal to the centre of the die. The outer (distal) sidewalls 394 are closer to the edge of the die.

[0088] As illustrated in FIG. 8, in a device structure according to a third embodiment, the cladding 390 is provided as a conformal layer or layers extending over the surface of the GaN-on-Si die, and extending over inner sidewalls of the pre-dicing trenches. The cladding 390 may comprise, e.g. one or more dielectric layers such as SiO.sub.2 or Si.sub.3N.sub.4. Optionally, the cladding further comprises a metal layer. The metal layer preferably acts as a barrier against electro-migration of contaminant ions. If a metal layer is provided, there would also be an overlying dielectric passivation layer, e.g. silicon nitride or silicon nitride to protect the metal layer against mechanical and environmental damage. The structures shown in FIGS. 6 to 8 may optionally include a seal ring, such as illustrated schematically in FIG. 4.

[0089] If required, the metal layer of the trench cladding 390 connects the substrate within the trench to a source electrode of the transistor, or, if a seal ring is provided, connects the substrate to metal layers of the seal ring.

[0090] FIGS. 9 to 13 show a series of simplified schematic cross-sectional diagrams to illustrate an exemplary process flow for fabrication of a nitride semiconductor device structure 400 comprising a lateral GaN transistor 414 according to an embodiment of the present invention, similar to that illustrated in FIG. 8, and further comprising a seal ring 480. The seal ring is similar to that illustrated in FIG. 4.

[0091] As illustrated in FIG. 9, device fabrication proceeds as conventionally, to completion of the on-chip interconnect structure (901) comprising the on-chip metallization layers and intervening dielectric layers (BEOL layers) forming the interconnect metallization for the GaN transistor 414 and the surrounding seal ring 480. Then, for structures 902 and 903, as shown in FIGS. 10 and 11 respectively, a pre-dicing trench structure 488 is defined in the region between the GaN die. The pre-dicing trench structure is formed by dry etching through to the silicon substrate, using a sequence of dry etch steps. For example, a first etch process removes any layers overlying the GaN epi-layers in the trench, as illustrated in FIG. 10, forming a first portion of the trench 488-1. Then a second etch process removes the GaN epi-layers in the trench, and removes a surface region of the silicon substrate, e.g. to etch several microns into the silicon substrate, to form a deeper trench structure 488-2 as illustrated in FIG. 11.

[0092] As illustrated in FIGS. 9 to 13, an inactive region 406 of the GaN epi-layers surrounds the 2DEG active regions 404 in the GaN epi-layers of the transistor structure, and the trench 488 extends through the inactive region of the GaN epi-layers. Thus, the trench 488 is separated from the edge of the active 2DEG region by the inactive area 406, and is positioned between the active region/area 404 of the GaN transistor and the dicing street 408 at the die edge.

[0093] In this embodiment, the trench is shown as having tapered or sloping sides formed by a first etch process and steep sides, e.g. as formed by an anisotropic etch, towards the bottom of the trench. At least part of the sides of the trench may alternatively be straight sided and/or tapered (sloped), depending on the type of etchant and etch process.

[0094] The trench lining or cladding 490 is then formed, as illustrated in FIG. 13, comprising at least one passivation layer and optionally a conductive metal layer. The trench lining covers at least the inner sidewalls or proximal sidewalls of the trench surrounding and spaced from the active region of the transistor. As illustrated schematically in FIG. 12, the trench lining comprises a plurality of conformally deposited passivation layers, such as a layer of silicon dioxide and/or a layer of silicon nitride, which are provided all over the exposed surfaces of the wafer, to seal the surface of the wafer. As illustrated schematically in FIG. 13, the conformal layers are then selectively removed to expose source and drain contact pads, and the conformal layers are also removed to expose part of the bottom of the trench and the trench sidewalls and die area closest to the dicing street. This clears the passivation dielectrics from the scribe street prior to wafer dicing, and leaves the layers of passivation dielectric conformally coating and sealing edges of the exposed backend dielectric layers and the exposed edges of the epi-layer stack. The wafer is subsequently diced, to singulate individual die, i.e. cut through any overlying BEOL layers, the GaN epi-layers and the silicon substrate between the pre-dicing trenches, using any suitable dicing method. For conventional wafer sawing, the remaining portion of the BEOL layers and epi-layers in the dicing street serve as sacrificial layers during dicing, to reduce risk of surface chipping or other dicing induced damage into the silicon substrate at the sawn edge 418.

[0095] As shown schematically, propagation of any dicing damage or cracks 482 near the sawn or cut edge of the die is blocked by the gap resulting from placement of trench near the die edge.

[0096] The passivation layers which protect exposed surfaces of the GaN epi-layers may be a dielectric such as silicon nitride or silicon dioxide. If provided, a conductive metal layer may be the same as that used for other on-chip metallization layers, and preferably provides a barrier layer against electro-migration of mobile ions. Thus, the trench lining or cladding forms a barrier layer to reduce risk of contaminant ions penetrating the active region and causing device parametric shifts over long term.

[0097] Where the trench lining comprises a conductive metal layer, the metal layer may be extended to connect the source of the transistor to the substrate, i.e. to ground the substrate. Alternatively, if the die comprises a seal ring, the metal layer may connect the substrate to metallization layers of a seal ring. Preferably a passivation layer of dielectric, e.g. silicon nitride is provided over the metal layer. Thus, the trench lining forms a protective layer over edges of the GaN epi-layer, and over edges of the BEOL layers, which would otherwise be exposed during conventional wafer dicing.

[0098] In the process flow described above, since the pre-dicing trench structure, and its protective trench lining, are formed after completion of on-chip interconnect and dielectric layers, wafer fabrication of the GaN-on-Si die can proceed as is conventional up to that point.

[0099] The additional steps required to form the trench structure comprise providing a suitable etch mask over the active device areas, exposing the areas to be trenched, and then removing layers of material within the trench by one or more Reactive Ion Etching (RIE) steps. For example a first etch step is performed to remove all oxide layers, etch stopping on the top of the GaN epi-layer stack. Then a second etch is performed to remove the GaN epi-layer stack within the trench. This etch is stopped well into the silicon substrate, e.g. 2 m or more below the interface between the silicon substrate and layer of the epi-layer stack. By way of example, the step of removing the GaN epi-layers from the trench uses an etching process, such as RIE, or preferably ICP (Inductively Coupled Plasma) or ECR (Electron Cyclotron Resonance) etching with a chlorine containing gas mixture, such as BCl.sub.3, SiCl.sub.4 plus an inert gas such as Ar, wherein gas mixtures and energies are selected to control the isotropy/anisotropy of the etch to produce steep or sloped sidewalls, as required. Preferably, the etch process is capable of cleanly exposing edges of the GaN epi-layers in the sidewalls of the trench without creating significant defects or etch damage, i.e. so as to avoid initiating cracks in the GaN epi-layers. As mentioned above, the sidewalls of the pre-dicing trench may have steep sides or be tapered, as appropriate, depending on the materials used for the trench lining. The trench lining may extend partly over the bottom of the trench. Alternatively, the trench lining may be provided only on the proximal (inner) sidewalls of the trench, and/or the trench lining may be removed from the bottom of the trench before subsequent dicing of the silicon substrate.

[0100] In a device structure 1000 comprising a lateral GaN transistor 1014 according to another embodiment, as shown in FIG. 14, the device structure has some elements similar to that shown in FIG. 5. However, instead of a pre-dicing trench being formed around the periphery of each individual die, in this embodiment, a single pre-dicing trench 1088 is etched along the scribe line between each die, and shared between adjacent die. If required, the trench may be etched across a substantial part of the width of the dicing street. After providing a trench cladding 1090 on proximal sidewalls of each die, i.e. as described with reference to device structures of the embodiments described above, e.g. with reference to FIGS. 9 to 13, the individual die are then singulated using any suitable dicing process, e.g. laser grooving through the substrate within the pre-dicing trench 1088.

[0101] As illustrated schematically in FIG. 15, a GaN-on-Si device structure 1100, according to yet another embodiment, comprises a large area high voltage/high current lateral GaN transistor which provides a trench structure for stress relief across the wafer, and within each die area. That is, the pre-dicing trench 1188 around the periphery of each die is extended to run through the dicing streets 1108 to relieve stress across the wafer, and reduce wafer bowing. Optionally, and in addition to the trench 1188 around the periphery of each die, a plurality of intra-die stress-relieving trenches 1191 are etched in x and y directions across each die. The intra-die stress relieving trenches are similarly structured to the pre-dicing trenches described above, in that they extend through the GaN epi-layer stack, several microns into the silicon substrate, and trench cladding is preferably provided to seal exposed edges of the layers of the GaN epi-layer stack. Each transistor die is thereby divided into a number of smaller areas, e.g. 45=20 areas, as illustrated schematically. For example, where the GaN device comprises a large area, multi-island transistor, such as described in U.S. Pat. No. 9,153,509, each smaller area defined trenches may accommodate a plurality of GaN transistor islands, or an individual transistor island. One or more overlying metallization layers, e.g. an on-chip metal layer and/or a post-processing layer such as copper Redistribution Layer (Cu RDL) is provided to interconnect individual islands.

[0102] In this structure, the inter-die and intra-die stress relieving trenches may be formed earlier in the process flow, e.g. before formation of the overlying BEOL metallization and dielectric layers. The trenches then divide the epi-layer stack into multiple smaller areas, so that the total integrated tensile stress across the wafer is relieved, and beneficially, wafer bowing is reduced. Wafer bowing tends to increase with increasing thickness of the GaN epi-layers, and this can create issues for focussing, alignment and registration in subsequent photo-lithography steps, particularly for large diameter substrate wafers. By mitigating wafer bowing, ideally substantially eliminating wafer bowing so the wafer lies flat, subsequent photo-lithography steps are facilitated.

[0103] Thus, nitride semiconductor device structures comprising high voltage, high current GaN power transistors, and methods of fabrication thereof, according to embodiments of the present invention are disclosed, wherein a GaN semiconductor device comprises a GaN epi-layer stack on a silicon substrate (GaN-on-Si die) and wherein pre-dicing trench structure are provided around each die, to reduce risk of GaN epi-layer cracking during die singulation and for improved device yield and reliability. Advantageously, a trench lining or cladding on inner sidewalls of the trench, comprising one or more dielectric layers, and optionally a metal layer, seals edges of the layers of the epi-layer stack, and edges of the back-end dielectric layers. Additionally, and optionally, further stress relieving intra-die trenches are provided to divide the epi-layer stack of each die into a plurality of regions, each comprising one or more transistor islands.

[0104] While nitride semiconductor device structures, according to embodiments of the present invention, have been described in detail with reference to lateral GaN transistors, such as a high voltage/high current GaN HEMTs, comprising GaN/AlGaN hetero-layer structures, it will be apparent that nitride semiconductor device structures according to alternative embodiments may comprise lateral GaN power transistors and/or diodes. More generally, a nitride semiconductor device comprises a III-nitride semiconductor, that is, a compound semiconductor which includes nitrogen and at least one group III element, such as GaN, AlGaN, AlN, InGaN, InAlGaN, and the nitride semiconductor device structure comprises a hetero-layer structure comprising first and second nitride semiconductor layers of different bandgaps, that forms an active region comprising a two dimensional electron gas (2DEG) region for transistors and/or diodes.

[0105] The device structures, and methods of fabrication thereof, described herein are particularly applicable to large area lateral GaN transistors and diodes for high current and high voltage applications, e.g. where it may be desirable to provide a relatively thick GaN epi-layer-stack, e.g. 6 m for increased breakdown voltage, on a low cost silicon substrate. The trench structure helps to reduce interlayer stresses resulting from lattice mismatch between the silicon substrate and the overlying GaN epi-layers, and which can cause significant wafer bowing (microns) over large diameter substrates. For large area die, e.g. 2 mm6 mm, or 10 mm10 mm or more, where significant tensile stresses may be present across the die area itself, intra-die trenches may also be provided for stress relief, i.e. to divide the die area into a plurality of smaller area, facilitate subsequent fabrication steps and to further reduce risk that defects can potentially propagate and cause cracking and/or delamination of the epi-layers from the substrate.

[0106] Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims.