PROCESS FLOW FOR A COMBINED CA AND TSV OXIDE DEPOSITION

Abstract

A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

Claims

1. A device comprising: a silicon substrate; a gate stack having source/drain regions at opposite sides thereof on the silicon substrate; a shallow trench isolation (STI) layer on the silicon substrate; a through silicon via (TSV) trench formed through the STI layer and the silicon substrate, and laterally separated from the gate stack; an isolation layer formed on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; a TSV formed in the TSV trench; a dielectric cap formed over the isolation layer and the TSV; and a source/drain contact formed through the dielectric cap and the isolation layer down to the source/drain regions.

2. The device according to claim 1, wherein a nitride layer is formed over the gate stack, the STI layer, and the silicon substrate prior to the TSV trench being formed.

3. The device according to claim 1, wherein the isolation layer is formed on the sidewalls of the TSV trench to a thickness of 15 nanometers (nm) to 500 nm.

4. The device according to claim 3, wherein the isolation layer is formed over the gate stack, the STI layer, and the silicon substrate to a thickness of 15 nm to 1000 nm.

5. The device according to claim 1, wherein the dielectric cap is formed to a thickness of 10 nm to 200 nm.

6. The device according to claim 1, wherein an additional isolation layer is formed on the isolation layer in the TSV trench to a thickness of 20 nm to 100 nm.

7. The device according to claim 6, wherein the additional isolation layer is formed on the isolation layer over the gate stack, the STI layer, and the silicon substrate to a thickness of 60 nm to 400 nm.

8. A device comprising: a gate stack, with source/drain regions at opposite sides thereof, and a shallow trench isolation (STI) layer on a silicon substrate; a nitride layer directly over the gate stack, the STI layer, and the silicon substrate; a through silicon via (TSV) trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; an isolation layer formed on an entirety of the nitride layer without any intervening layer between the isolation layer and nitride layer when viewed in cross-section, such that the isolation layer is formed on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; a TSV formed in the TSV trench; a dielectric cap formed over the isolation layer and the TSV; and a source/drain contact formed through the dielectric cap and the isolation layer down to the source/drain contract regions.

9. The device according to claim 8, wherein the isolation layer comprises tetraethyl orthosilicate (TEOS).

10. The device according to claim 8, wherein the nitride layer is formed over the gate stack, the STI layer, and the silicon substrate prior to the TSV trench being formed.

11. The device according to claim 8, wherein the isolation layer is formed on the sidewalls of the TSV trench to a thickness of 15 nanometers (nm) to 500 nm.

12. The device according to claim 11, wherein the isolation layer is formed over the gate stack, the STI layer, and the silicon substrate to a thickness of 15 nm to 1000 nm.

13. The device according to claim 8, wherein the dielectric cap is formed to a thickness of 10 nm to 200 nm.

14. The device according to claim 8, wherein an additional isolation layer is formed on the isolation layer in the TSV trench to a thickness of 20 nm to 100 nm.

15. The device according to claim 14, wherein the additional isolation layer is formed on the isolation layer over the gate stack, the STI layer, and the silicon substrate to a thickness of 60 nm to 400 nm.

16. The device according to claim 8, wherein the TSV comprises: a barrier layer on the isolation layer; a seed layer on the barrier layer; and a conductive material filling the trench of the TSV.

17. The device according to claim 16, wherein the barrier layer comprises titanium (Ti), tantalum (Ta), titanium nitride (TiN), TaN/Ta, or a magnesium-based metal (MnM) to a thickness of 5 nm to 50 nm.

18. The device according to claim 8, wherein the dielectric cap comprises a barrier low-k oxide (BLOK).

19. A device comprising: a gate stack, with source/drain regions at opposite sides thereof, and a shallow trench isolation (STI) layer on a silicon substrate; a nitride layer over the gate stack, the STI layer, and the silicon substrate; a through silicon via (TSV) trench, laterally separated from the gate stack, through the nitride layer, the STI layer, and the silicon substrate with a mask; a first isolation layer on sidewalls of the TSV trench to a thickness of 15 nanometers (nm) to 500 nm and over the nitride layer to a thickness of 15 nm to 1000 nm; a second isolation layer on the first isolation layer in the TSV trench to a thickness of 20 nm to 100 nm and over the first isolation layer over the nitride layer to a thickness of 60 nm to 400 nm; a barrier layer on the second isolation layer in the TSV trench and over the second isolation layer over the nitride layer; a seed layer on the barrier layer; a conductive material filling a remainder of the TSV trench; a dielectric cap formed over the second isolation layer, the barrier/seed layer, and the conductive material to a thickness of 10 nm to 200 nm; and a source/drain contact through the dielectric cap, the first and second isolation layers, and the nitride layer down to the source/drain contract regions.

20. The device according to claim 19, wherein the second isolation layer has a thickness of 50 nm to 250 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

[0014] FIGS. 1 through 13 schematically illustrate sequential steps of a method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

[0015] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term about.

[0016] The present disclosure addresses and solves the current problem of two separate deposition steps, e.g., an isolation layer deposition and TSV liner deposition, attendant upon forming a TSV for 3D integration. By forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process, the problems of PMD thickness and non-uniformity across the wafer can be reduced. In addition, the overall cost may be reduced by removing the TSV CMP stop layer and the isolation layer CMP step and by reducing the number of inspection/measurement steps, the oxide open step and the thickness of the TSV mask, all associated with previous process flows.

[0017] Methodology in accordance with embodiments of the present disclosure includes providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate. A TSV trench, laterally separated from the gate stack, is formed through the STI layer and the silicon substrate. An isolation layer is formed on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate. A TSV is formed in the TSV trench. A dielectric cap is formed over the isolation layer and the TSV. A source/drain contact is formed through the dielectric cap and the isolation layer down to the source/drain contract regions.

[0018] Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0019] FIGS. 1 through 13 schematically illustrate sequential steps of a method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process, in accordance with an exemplary embodiment. Adverting to FIG. 1, a gate stack 101 with source/drain regions 103 at opposite sides thereof and an STI layer 105 are formed on a silicon substrate 107. Next, a nitride layer 201, e.g., TPEN, NPEN, or CPEN, is formed to a thickness of 20 nm to 40 nm over the gate stack 101, the STI layer 105, and the silicon substrate 107, as depicted in FIG. 2. Alternatively, the nitride layer 201 may be removed from the process flow.

[0020] Adverting to FIG. 3, a TSV mask/resist layer 301 is formed over the nitride layer 201. Next, a 0.5 to 25 wide opening 303, laterally separated from the gate stack 101, is patterned in the resist layer 301. A TSV trench 401 is then formed by etching, e.g., by DRIE, a 0.5 to 25 wide cavity 403 in the nitride layer 201 and the STI layer 105 down to the silicon substrate 107, as illustrated in FIG. 4. Consequently, 2.5 to 4.5 of the resist layer 301 are lost due to the etching process. Adverting to FIG. 5, the TSV trench 401 is further formed by etching, e.g., by DRIE, a 0.5 to 25 wide and 20 to 200 deep cavity 501 into the silicon substrate 107 below the cavity 403. As a result, a further 1 to 2 of the resist layer 301 are lost due to the subsequent etching process. The minimal resist loss during the TSV trench 401 formation processes allows the overall thickness of the TSV mask/resist layer 301 to be reduced, which reduces the overall cost.

[0021] Adverting to FIG. 6, the TSV mask resist 301 is stripped and the TSV trench 401 is cleaned (not shown for illustrative convenience). Next, an isolation layer 701, e.g., tetraethyl orthosilicate (TEOS), is formed to a thickness of 15 nm to 500 nm, e.g., 200 nm, on the sidewalls of the TSV trench 401 and to a thickness of 15 nm to 1000 nm, e.g., 450 nm, on the nitride layer 201, as depicted in FIG. 7. An optional isolation layer 801, e.g., TEOS, may also be formed in the TSV trench 401 to a thickness of 20 nm to 100 nm and on the isolation layer 701 over the nitride layer 201 to a thickness of 60 nm to 400 nm, as depicted in FIG. 8.

[0022] Next, a TSV is formed by first forming a barrier layer 901, e.g., Ti, Ta, TiN, TaN/Ta, or MNM, on the optional isolation layer 801 to a thickness of 5 nm to 50 nm, as depicted in FIG. 9. A seed layer 903, e.g., Cu, is deposited by physical vapor deposition (PVD) to a thickness of 50 nm to 800 nm. Thereafter, the remainder of the TSV trench 401 is filled with a conductive material 1001, e.g., Cu, as illustrated in FIG. 10. The conductive material 1001 is then annealed at a temperature of 100 C. to 450 C. (not shown for illustrative convenience). The temperature may vary depending on the conductive material used to fill the TSV trench 401. Adverting to FIG. 11, the conductive material 1001, the barrier layer 901, the seed layer 903, and the optional isolation layer 801 are planarized, e.g., by CMP, until the final thickness of the optional isolation layer 801 is 50 nm to 250 nm. Alternatively, when the optional isolation layer 801 is absent, the conductive material 1001, the barrier layer 901, the seed layer 903, and the isolation layer 701 are planarized, e.g., by CMP, until the final thickness of the isolation layer 701 is 20 nm to 950 nm (not shown for illustrative convenience). Next, a dielectric cap 1201, e.g., BLOK, is formed on the conductive material 1001, the barrier layer 901, the seed layer 903, and the optional isolation layer 801 to a thickness of 10 nm to 200 nm, as depicted in FIG. 12.

[0023] Adverting to FIG. 13, a contact 1301, e.g., filled with tungsten, is formed in a conventional manner through the optional isolation layer 801, the isolation layer 701, and the optional nitride layer 201 down to the source/drain region 103. An additional dielectric cap 1303, e.g., BLOK, is then deposited on the dielectric cap 1201.

[0024] The embodiments of the present disclosure can achieve several technical effects including reducing the problem of PMD thickness and non-uniformity across a wafer by forming the TSV isolation layer and the transistor to BEOL isolation layer during a single deposition process. In addition, the overall cost may be reduced by removing the TSV CMP stop layer and the isolation layer CMP step and by reducing the number of inspection/measurement steps, the oxide open step and the TSV mask resist thickness, all associated with prior process flows. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure enjoys industrial applicability in any of various types of semiconductor devices having a TSV module, particularly those intended for 3D integration in 130 nm technology nodes and below.

[0025] In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.