JET ABLATION DIE SINGULATION SYSTEMS AND RELATED METHODS

Abstract

Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.

Claims

1. A method of forming a substrate with one or more semiconductor die, the method comprising: forming a plurality of semiconductor devices across a first surface of a semiconductor wafer; applying a metal layer on a second surface of the semiconductor wafer; applying a passivation layer over the plurality of semiconductor devices and the first surface of the semiconductor wafer; etching the metal layer to form a patterned array of the metal layer and an array of die streets exposing portions of the semiconductor wafer; partially etching the semiconductor wafer exposed in the array of die streets starting from the second surface of the semiconductor wafer toward the passivation layer; and ablating away any remaining material of the semiconductor wafer and passivation layer within the array of die streets to separate the substrate with one or more semiconductor die from the semiconductor wafer.

2. The method of claim 1, wherein the passivation layer comprises one or more of a silicon nitride, oxide, metal electrical test structure, electrical test pad, silicon dioxide, polyimide, metal pad, under bump metallization, or any other material configured to one of facilitate thermal connection between the one or more semiconductor die or protect the one or more semiconductor die from contaminants.

3. The method of claim 1, wherein the passivation layer is a non-plasma etchable layer.

4. The method of claim 1, wherein the passivation layer is configured to facilitate electrical connection between the one or more semiconductor die.

5. The method of claim 1, wherein partially etching the semiconductor wafer comprises only partially etching the semiconductor wafer.

6. The method of claim 1, further comprising fully etching the semiconductor wafer.

7. The method of claim 1, further comprising a plurality of test structures within the array of die streets.

8. A method of forming one or more semiconductor die, the method comprising: forming an array of semiconductor devices distributed across a first surface of a semiconductor substrate; forming an edge ring on a second surface of the semiconductor substrate; patterning a metal array on a portion of the second surface of the semiconductor substrate, wherein the semiconductor substrate is exposed at a plurality of die streets; forming a passivation layer over the first surface of the semiconductor substrate including the array of semiconductor devices; and singulating the one or more semiconductor die by ablating away the semiconductor substrate, the passivation layer, and metal structures within the plurality of die streets.

9. The method of claim 8, wherein the passivation layer comprises one or more of a silicon nitride, oxide, metal electrical test structure, electrical test pad, silicon dioxide, polyimide, metal pad, under bump metallization, or any other material configured to one of facilitate thermal connection between the one or more semiconductor die or protect the one or more semiconductor die from contaminants.

10. The method of claim 8, wherein the passivation layer is a non-plasma etchable layer.

11. The method of claim 8, wherein the passivation layer is configured to facilitate electrical connection between the one or more semiconductor die.

12. The method of claim 8, wherein the semiconductor substrate is less than 50 microns thick.

13. The method of claim 8, wherein the semiconductor substrate is less than 25 microns thick.

14. A method of forming one or more semiconductor die, the method comprising: thinning a portion of a semiconductor wafer at a second surface of the semiconductor wafer to form an edge ring on the second surface of the semiconductor wafer; patterning a metal array along a plurality of die streets on a thinned portion of the second surface of the semiconductor wafer to expose a portion of the semiconductor wafer in the plurality of die streets; forming a plurality of semiconductor devices one of on or within a first surface of the semiconductor wafer; applying a passivation layer over the plurality of semiconductor devices; etching the semiconductor wafer exposed in the plurality of die streets at least partially toward the passivation layer; and singulating the one or more semiconductor die by ablating away the passivation layer within the plurality of die streets.

15. The method of claim 14, wherein the passivation layer comprises one or more of a silicon nitride, oxide, metal electrical test structure, electrical test pad, silicon dioxide, polyimide, metal pad, under bump metallization, or any other material configured to one of facilitate thermal connection between the one or more semiconductor die or protect the one or more semiconductor die from contaminants.

16. The method of claim 14, wherein the passivation layer is a non-plasma etchable layer.

17. The method of claim 14, wherein the passivation layer is configured to facilitate electrical connection between the one or more semiconductor die.

18. The method of claim 14, wherein the portion of the semiconductor wafer is thinned to less than 50 microns thick.

19. The method of claim 14, wherein the portion of the semiconductor wafer is thinned to less than 25 microns thick.

20. The method of claim 14, wherein a portion of the semiconductor wafer is ablated away with the passivation layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Implementations will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:

[0028] FIG. 1 is a side view of a semiconductor substrate with a passivation layer and a back metal layer thereon;

[0029] FIG. 2 is a side view of the substrate of FIG. 1 following patterning of the back metal layer;

[0030] FIG. 3 is a side view of the substrate of FIG. 2 following etching of the substrate material down to the passivation layer;

[0031] FIG. 4 is a side view of the substrate of FIG. 3 following demounting and mounting during jet ablation;

[0032] FIG. 5 is a side view of the two singulated die illustrated in FIG. 4 following ablation of the passivation layer.

DESCRIPTION

[0033] This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended jet ablation systems and related methods will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such jet ablation systems and related methods, and implementing components and methods, consistent with the intended operation and methods.

[0034] For semiconductor die that are less than 50 microns in thickness, particular processing challenges exist. Die handling, die strength, and performing processing operations with the die all present specific challenges, as die and wafer breakage can significantly reduce yield and/or affect device reliability. Die strength is negatively affected by traditional singulation options like sawing which induce die chipping and cracking along the die streets. These chips and cracks formed during the sawing process can eventually propagate during operation and reliability testing causing the die to fail.

[0035] Referring to FIG. 1, in various implementations disclosed in this document, the semiconductor substrate 2 includes a plurality of semiconductor die 4 (two are subsequently illustrated in the drawings) that have been processed using a semiconductor fabrication process to form one or more semiconductor devices therein or thereon (not shown). Following the completion of the fabrication process (or during some portion of it, in some implementations), the semiconductor substrate 2 is thinned on a side of the semiconductor substrate 2 that is opposite the side on which the one or more semiconductor devices have been formed to a desired substrate thickness 6. The thinning process takes place using backgrinding, lapping, wet etching, any combination thereof, or any other technique for removing backside damage and/or the material of the semiconductor substrate 2 substantially uniformly across the largest planar surface of the substrate. The semiconductor substrate 4 may be in various implementations, by non-limiting example, single crystal silicon, polysilicon, amorphous silicon, glass, sapphire, ruby, gallium arsenide, silicon carbide, silicon-on-insulator, and any other semiconductor substrate type.

[0036] In various implementations, the thinning process may create an edge ring around the wafer (like that present in the TAIKO backgrinding process marketed by Disco Hi-Tec America, Inc. of Santa Clara, California). The edge ring acts to structurally support the wafer following thinning so that no wafer carrier may need to be utilized during subsequent processing steps. In various implementations, the thinning process may be carried out after the semiconductor substrate 2 has been mounted to a backgrinding tape whether an edge ring is formed during backgrinding or not. A wide variety of backgrinding tapes may be employed in various implementations, including those that are compatible with subsequent plasma etching operations.

[0037] Following the thinning process, the various die 4 formed in the semiconductor substrate 2 need to be singulated from one another so they can be subsequently packaged into semiconductor packages. In various implementations, following the thinning process a back metal layer 10 is applied to the semiconductor die through, by non-limiting example, sputtering, evaporation, or another metal deposition process. In various implementations, the deposition process is conducted while the wafer is either supported by an edge ring or supported by the backgrinding tape. In other implementations, however, the substrate may be demounted from the backgrinding tape and mounted to another support tape for subsequent processing steps.

[0038] FIG. 1 illustrates an implementation of a semiconductor substrate 2 following the back metal deposition process and the thinning process. In various implementations, as illustrated, the substrate 2 is coupled with a tape 14 (which may be the backgrinding or other support tape in various implementations). In other implementations, however, at this stage in the process the wafer may not be coupled with a tape 14 (such as when an edge ring is being used). As illustrated, the one or more semiconductor die 4 (not yet separately visible) are covered by a layer of passivation material 16. In various implementations the passivation material 16 may include, by non-limiting example, silicon nitride, oxides, metal electrical test structures, electrical test pads, silicon dioxide, polyimides, metal pads, residual underbump metallization (UBM), any combination thereof, and any other layer or material capable of facilitating electrical or thermal connection between the one or more semiconductor die and/or protecting the one or more semiconductor die from contaminants. Because of this, the term passivation material and passivation layer, as used herein, includes any of the aforementioned materials whether the material was deposited to act as a passivating material or whether the material merely forms a non-plasma etchable portion or layer in the die street region.

[0039] As illustrated in FIG. 1, the total thickness 8 of the semiconductor substrate 2 is the additive thickness of the substrate thickness 6, the thickness 18 of the back metal 10, and the thickness 12 of the passivation material 16. In various implementations, thickness of the back metal may vary from between about 1 micron to about 15 microns. In particular implementations, the thickness of the back metal may be between about 1 micron to about 3 microns. In various implementations, the total thickness 8 of the semiconductor substrate 2 may be less than about 50 microns. In particular implementations, the total thickness 8 of the semiconductor substrate may be between about 25 microns to about 35 microns. In various implementations, the total thickness 8 may be about 25 microns.

[0040] Referring to FIG. 2, the substrate 2 is illustrated following patterning of the back metal layer 10. The patterning may be accomplished using any of a wide variety of photolithography processes involving the application of photoresist; exposure, development, then removal of the photoresist; etching of the back metal 10 using an appropriate etchant, and removal of the photoresist. With the substrate material exposed following etching and patterning of the back metal layer 10 in the patterned areas/die streets 20 of the back metal layer 10, the material of the substrate is ready for etching. In various implementations, the substrate material then be etched all the way down to or toward the passivation layer 16. In other implementations, however, the etching may be conducted partially through, or substantially through the thickness 6 of the substrate 2 down to or toward the passivation layer 16 (the etching may be carried out using a plasma etching processes in various implementations). Generally, the plasma etch chemistries used to etch the material of the substrate 2 do not etch the materials of the passivation layer or any metal structures in the street (electrical test/alignment features, etc.), leaving the plurality of semiconductor die still unsingulated after the etching of the substrate. The semiconductor die 4 following etching of the substrate 2 are illustrated in FIG. 3.

[0041] Referring to FIG. 4, the substrate 2 of FIG. 3 is illustrated after having been demounted from the original (first) tape 14 and mounted to a new tape 22 (which may be a picking tape in various implementations). As illustrated, the die 4 are still coupled together through at least the material of the passivation layer 16. In those implementations where the substrate has been only partially singulated or substantially singulated, some portion of the semiconductor material may also still couple the plurality of die together. For those implementations where an edge ring is used, the edge ring may still work to support the die 4 during the demounting and mounting process. In some implementations where an edge ring is employed and the substrate is being processed without being mounted to a backgrinding tape, the substrate may be flipped over and mounted without first being demounted following the etching step.

[0042] FIG. 4 illustrates a fluid jet 24 being applied to the location of the street 20 between the semiconductor die 40, causing the material of the passivation layer 16 (any other metal structures remaining in the street 20) to ablate away. While water may be used as being the liquid used for ablation, other fluids, gases, combinations of fluids, and combinations of fluids and gases may be employed in various method implementations.

[0043] While in various implementations and as illustrated in FIG. 4, the fluid jet 24 is applied to the passivation layer side (second side) 26 of the substrate 2 after the substrate 2 has been flipped over following etching of the substrate, in other implementations, the substrate 2 may not be flipped over and the fluid jet 24 may be applied to the street region to ablate away the material of the passivation layer from the back metal side (first side) 28 of the substrate. While the substrate 2 in FIGS. 2-4 is illustrated as having the full thickness 6 of the material of the substrate 2 etched through, in some implementations as previously discussed, a portion of the thickness of the substrate material may be left unetched to add sufficient strength to the substrate to allow it to be demounted, flipped over, and mounted. The jet ablation process may then be applied and used to remove the passivation material and the remaining material of the substrate in the street 20 as well. In some implementations, however, the substrate 2 may not be demounted and flipped over before application of jet ablation. In such implementations, it has been observed that the material of the passivation layer is driven into the tape and successfully separates the various die under the pressure of the fluid jet.

[0044] Referring to FIG. 5, the semiconductor die 4 are illustrated following jet ablation of the passivation material 16. They may now be picked from the support tape 22 and prepared for subsequent packaging operations.

[0045] As illustrated in FIGS. 2 and 3, the patterned back metal is used as the patterning for the substrate etching process. Because of this, no additional photolithographic processing may be needed to carry out the substrate etching process. In some implementations, however, a photolithography step could be used to protect metal or other materials on the die during the jet ablation process. Also, because the material of the semiconductor substrate 2 works to guide the flow of the water during the water jet ablation process (i.e., through resisting the flow of fluid, the substrate material causes the passivation material to yield under the pressure of the fluid stream or focuses the energy of the fluid stream on the passivation material), no additional photolithographic steps may need to be carried out to facilitate the ablation process. This reduction in photolithographic steps reduces the number of total processing steps involving the wafer following the thinning process which can increase the overall yield of the process through reducing substrate breakage. Furthermore, because it is the jet ablation used to finish fully clearing out the street areas, no special designs (like drop out die and/or use of partial die) need to be added to the design, thereby increasing total die per wafer. Furthermore, no special street designs that include no electrical test or alignment features may need to be used to enable the plasma substrate etching process. Also, not using any saw singulating process may result in increase in good die and increases in die strength due to reductions in die chipping and cracking induced during sawing processes.

[0046] In places where the description above refers to particular implementations of jet ablation systems and related methods and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other jet ablation systems and related methods.