SPLIT GATE POWER SEMICONDUCTOR FIELD EFFECT TRANSISTOR

Abstract

The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.

Claims

1-7. (canceled)

8. A split gate planar IGBT structure, comprising: a collector electrode at the bottom; a heavily doped collector region of a second conductivity type; a buffer region of a first conductivity type, the buffer region being on the top of the collector region; a lightly doped drift region of the first conductivity type, the lightly doped drift region being on the top of the buffer region; a heavily doped diffusion of the second conductivity type, the heavily doped diffusion being contacted by an emitter electrode; a body region of the second conductivity type, the body region being connected to the emitter electrode through the heavily doped diffusion; a heavily doped emitter region of the first conductivity type, the heavily doped emitter region being contacted by the emitter electrode; a gate dielectric, covering the surface of the body region and forming a channel between the heavily doped emitter region and the lightly doped drift region; a split gate electrode, the split gate electrode being on the top of the gate dielectric; a thin dielectric layer, covering the surfaces of the split gate and the lightly doped epitaxial layer; a semi-insulating field plate the semi-insulating field plate being on the top of the thin dielectric layer and contacted by the emitter electrode at the side wall; an interlayer dielectric (ILD), the interlayer dielectric being on the top of the semi-insulating field plate; and the emitter electrode, the emitter electrode being in contact holes and on the top of the ILD.

9. The split gate planar IGBT structure according to claim 8, wherein the collector and the emitter electrodes are metal or metal suicide.

10. The split gate planar IGBT structure according to claim 8, wherein the gate dielectric is silicon oxide.

11. The split gate planar IGBT structure according to claim 8, wherein the split gate electrode is at least one of polysilicon, metal and metal silicide.

12. The split gate planar IGBT structure according to claim 8, wherein the thin dielectric layer is silicon oxide.

13. The split gate planar IGBT structure according to claim 8, wherein the semi-insulating field plate comprises titanium nitride, polysilicon and amorphous silicon.

14. The split gate planar IGBT structure according to claim 8, wherein the ILD is silicon oxide.

15. A method for manufacturing a split gate planar power MOSFET structure, comprising (1) forming a lightly doped epitaxial layer of a first conductivity type on the top of a heavily doped substrate of the first conductivity type by epitaxial growth, (2) forming a heavily doped diffusion of a second conductivity type by ion implantation and thermal diffusion, (3) forming a gate dielectric, forming a gate electrode by deposition, and patterning the gate dielectric and the gate electrode, (4) forming a body region of the second conductivity type by self-aligned ion implantation and thermal diffusion, (5) forming a split gate by patterning the gate electrode and the gate dielectric, (6) forming a heavily doped source electrode of the first conductivity type by ion implantation and annealing, and depositing a thin dielectric layer, a semi-insulating field plate and an ILD, (7) patterning the ILD, the semi-insulating field plate and the thin dielectric layer to form contact holes and (8) forming a source electrode at the bottom, the surface and the drain electrode.

16. The manufacturing method according to claim 15, wherein the split gate is patterned by photolithography and etching.

17. The manufacturing method according to claim 15, wherein the ion implantation is optionally carried out after the split gate is etched so as to increase the doping concentration of the upper part of the n epitaxy.

18. The manufacturing method according to claim 15, wherein the ILD, the semi-insulating field plate and the thin dielectric layer are patterned by photolithography and etching simultaneously.

19. A method for manufacturing a split gate planar IGBT structure, comprising (1) starting with a lightly doped substrate wafer of a first conductivity type, (2) forming a heavily doped diffusion of a second conductivity type by ion implantation and thermal diffusion, (3) forming a gate dielectric, forming a gate electrode through deposition, and patterning the gate dielectric and the gate electrode, (4) forming a body region of the second conductivity type by self-aligned ion implantation and thermal diffusion, (5) forming a split gate by patterning the gate electrode and the gate dielectric, (6) forming a heavily doped emitter region of the first conductive type by implantation and annealing, and depositing a thin dielectric layer, a semi-insulating field plate and an ILD, (7) patterning the ILD, the semi-insulating field plate and the thin dielectric layer to form contact holes, and forming an emitter electrode on the surface and (8) thinning down the substrate wafer, forming a buffer layer of the first conductivity type by ion implantation and annealing, forming a heavily doped collecting region by ion implantation and annealing, and forming a collector electrode at the bottom.

20. The manufacturing method according to claim 19, wherein the split gate is patterned by photolithography and etching.

21. The manufacturing method according to claim 19, wherein the ion implantation is optionally carried out after the split gate is etched so as to increase the doping concentration of the upper part of the n epitaxy.

22. The manufacturing method according to claim 19, wherein the ILD, the semi-insulating field plate and the thin dielectric layer are patterned simultaneously by photolithography and etching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0078] FIG. 1 is a cross sectional view of a power MOSFET structure in the prior art.

[0079] FIG. 2 is a cross sectional view of another power MOSFET structure in the prior art.

[0080] FIG. 3 is a cross sectional view of a further power MOSFET structure in the prior art.

[0081] FIG. 4 is a cross sectional view applied in a power MOSFET of the present invention.

[0082] FIG. 5 is a cross sectional view applied in an IGBT of the present invention.

[0083] FIG. 6A-FIG. 6H show the critical process steps of the power MOSFET previously shown in FIG. 4.

[0084] FIG. 7A-FIG. 7H show the critical process steps of manufacturing the IGBT previously shown in FIG. 5.

DETAILED DESCRIPTION

[0085] FIG. 1 is a cross sectional view of a power MOSFET structure in the prior art. A gate electrode (21) is on the top of a gate dielectric (31), and the gate dielectric (31) covers the entire surface of an n.sup.-epitaxy (14).

[0086] FIG. 2 is a cross sectional view of another power MOSFET structure in the prior art. The device has a split gate (21) and a gate dielectric (31) below the gate (21). Only a small portion of the surface of the n.sup.-epitaxy (14) is covered by the gate dielectric (31), and the remaining surface is covered by an interlayer dielectric (ILD) (32).

[0087] FIG. 3 is a cross sectional view of a further power MOSFET structure in the prior art. The device has split gates (21) and a dummy gate (22) between the split gates (21). The dummy gate (22) is connected to a source electrode (22) and is isolated from the split gates (21) through an ILD (32).

[0088] FIG. 4 is a cross sectional view of the present invention implemented in a power MOSFET. The planar power MOSFET structure comprises a drain electrode (23) at the bottom; an n.sup.+ substrate (15); an n.sup.-epitaxy (14) on the top of the n.sup.+ substrate (15); a p.sup.+ diffusion (12) which is contacted by a source electrode (22); a p-type body region (13) which is connected to the source electrode (22) through the p.sup.+ diffusion (12); an n.sup.+ source (11) which is contacted by the source electrode (22); a gate dielectric (31) which covers the surface of the p-type body region (13) and forms a channel between the n.sup.+ source (11) and the n.sup.-epitaxy (14); a split gate electrode (21) on the top of the gate dielectric (31); a thin dielectric layer (33) which covers the surfaces of the split gate (21) and the n.sup.-epitaxy (14); a semi-insulating field plate (34) which is on the top of the thin dielectric layer (33) and is contacted by the source electrode (22) at the side wall; an interlayer dielectric (ILD) (32) on the top of the semi-insulating field plate (34); and the source electrode (22) which is in contact holes (41) and on the top of the ILD (32). The source electrode (22) and the drain electrode (23) are generally metal or metal silicide. The gate dielectric (31) is generally silicon oxide, but other high dielectric constant materials (e.g. aluminum oxide, oxynitride and hafnium oxide) can also be used as the gate dielectric (31). The gate electrode (21) of the device is generally polysilicon, because it is suitable for the self-aligned high-temperature process. However, metal or metal silicide can also be used for the gate electrode (21) for the object of minimizing the gate resistance. The thin dielectric layer (33) is generally silicon oxide, but other dielectric materials can also be used for the object of isolation. The ILD (32) is also used for isolation, and the ILD (32) is generally silicon oxide. The semi-insulating field plate (34) can be made of any high resistivity material, including, but not limited to titanium nitride, polysilicon and amorphous silicon.

[0089] FIG. 5 is a cross sectional view of the present invention implemented in an IGBT. The structure of the IGBT is similar to that of the power MOSFET structure as previously shown in FIG. 4. In the IGBT, an emitter electrode (24) instead of the source electrode (22) is positioned on the surface, and a collector electrode (25) instead of the drain electrode (23) is positioned at the bottom. The n.sup.+ substrate (15) is not present in the IGBT, but an n buffering region (16) and a p.sup.+ collecting region (17) are positioned below an n.sup. drift region (14).

[0090] FIG. 6A-FIG. 6H show the critical process steps of manufacturing the power MOSFET as previously shown in FIG. 4. The manufacturing process comprises (1) forming the n.sup.-epitaxy (14) on the top of the n.sup.+ substrate (15) via epitaxial growth; (2) forming the p.sup.+ diffusion (12) by implantation and main diffusion; (3) forming the gate dielectric (31), forming the gate electrode (21) by deposition, and patterning both the gate dielectric (31) and the gate electrode (21); (4) forming the p-type body region (13) by self-aligned implantation and main diffusion; (5) forming the split gate (21) by patterning the gate electrode (21) and the gate dielectric (31); (6) forming the n.sup.+ source electrode (11) by implantation and annealing, and depositing the thin dielectric layer (33), the semi-insulating field plate (34) and the ILD (32); (7) patterning the ILD (32), the semi-insulating field plate (34) and the thin dielectric layer (33) to form contact holes (41); and (8) forming the source electrode (22) on the surface and forming the drain electrode (23) at bottom. In the manufacturing process, the split gate (21) is formed by photolithography and then etching. Such photolithography generally needs an extra mask. In addition, after the split gate (21) is formed, the ion implantation step can optionally be added before the n.sup.+ source electrode (11) is formed, to increase the doping concentration of the upper part of the n.sup.-epitaxy (14), and therefore produce a reduced on-resistance. The ILD (32), the semi-insulating field plate (34) and the thin dielectric layer (33) can be subjected to mask lithography applied for the contact holes (41), then etched and patterned together.

[0091] FIG. 7A to FIG. 7H show the critical manufacturing process steps of the IGBT previously shown in FIG. 5. The manufacturing steps are similar to those shown in FIG. 6A to FIG. 6H. During the manufacturing of the IGBT, the process starts with the lightly doped n.sup. substrate wafer (14) instead of n.sup.-epitaxy (14). The process is the same as the process of the power MOSFET, until an emitter electrode (24) is formed on the surface, as shown in FIG. 7G. After this step, the n.sup. substrate wafer (14) is thinned down, and an n buffer region (16) is formed by ion implantation and annealing at the rear side. A p.sup.+ collector region (17) is subsequently formed by ion implantation and annealing at the rear side. Finally, a collector (25) is formed at the rear side of the wafer, as shown in FIG. 7H.