CERAMIC ELECTRONIC DEVICE WITH MULTILAYER CHIP HAVING CERTAIN Sn DISTRIBUTION

Abstract

A ceramic electronic device includes a multilayer chip comprising alternating internal electrode layers and dielectric layers stacked in a stacking direction. First and second external electrodes are provided on opposing end surfaces of the chip. The internal electrode layers include first and second internal electrodes, connected respectively to the first and second external electrodes. The multilayer chip includes a first outer layer section, a second outer layer section, and a center section in the stacking direction. The Sn concentration in the dielectric layers of the first outer layer section is lower than that in the center section.

Claims

1. A ceramic electronic device comprising: a multilayer chip including a plurality of internal electrode layers and a plurality of dielectric layers, the plurality of internal electrode layers and the plurality of dielectric layers being alternately stacked in a stacking direction; a first external electrode provided at a first end surface of the multilayer chip; and a second external electrode provided at a second end surface of the multilayer chip, the second end surface opposing the first end surface, wherein the plurality of internal electrode layers includes a plurality of first internal electrode layers and a plurality of second internal electrode layers, each of the plurality of first internal electrode layers being connected to the first external electrode, each of the plurality of second internal electrode layers being connected to the second external electrode, wherein the multilayer chip includes a first outer layer section, a second outer layer section, and a center section, the first outer layer section extending from a top surface of the multilayer chip in the stacking direction, the second outer layer section extending from a bottom surface of the multilayer chip in the stacking direction, the center section being disposed between the first outer layer section and the second outer layer section in the stacking direction, and wherein the Sn concentration in the dielectric layers of the first outer layer section is smaller than that in the dielectric layers of the center section.

2. The ceramic electronic device of claim 1, wherein the Sn concentration in dielectric layers of the second outer layer section is smaller than that in the dielectric layers of the center section.

3. The ceramic electronic device of claim 1, wherein the multilayer chip includes a capacity section, a first side margin and a second side margin, the first internal electrode layers and the second internal electrode layers, as viewed in the stacking direction, overlapping each other in the capacity section, the first side margin being disposed between the first end surface of the multilayer chip and the capacity section, the second side margin being disposed between the second end surface of the multilayer chip and the capacity section, and wherein, at a region overlapping the first side margin and the first outer layer section, the Sn concentration in the dielectric layers is smaller than that in the dielectric layers of the center section.

4. The ceramic electronic device of claim 3, wherein, at a region overlapping the first side margin and the second outer layer section, the Sn concentration in the dielectric layers is smaller than that in the dielectric layers of the center section.

5. The ceramic electronic device of claim 1, wherein the first outer layer section occupies 5% or more of the multilayer chip in the stacking direction.

6. The ceramic electronic device of claim 5, wherein the first outer layer section occupies 10% or more of the multilayer chip in the stacking direction.

7. The ceramic electronic device of claim 1, wherein the first outer layer section occupies 40% or less of the multilayer chip in the stacking direction.

8. The ceramic electronic device of claim 7, wherein the first outer layer section occupies 30% or less of the multilayer chip in the stacking direction.

9. The ceramic electronic device of claim 8, wherein the first outer layer section occupies 20% or less of the multilayer chip in the stacking direction.

10. The ceramic electronic device of claim 1, wherein a continuity modulus of the plurality of internal electrode layers in the first outer layer section is greater than that of the plurality of internal electrode layers in the center section.

11. The ceramic electronic device of claim 1, wherein the continuity modulus of the plurality of internal electrode layers in the second outer layer section is greater than that of the plurality of internal electrode layers in the center section.

12. The ceramic electronic device of claim 10, wherein the continuity modulus of the plurality of internal electrode layers in the first outer layer section is 90% or greater.

13. The ceramic electronic device of claim 1, wherein thicknesses of the plurality of internal electrodes are 0.01 m or more and 5 m or less.

14. The ceramic electronic device of claim 13, wherein the thicknesses of the plurality of internal electrodes are 0.05 m or more and 3 m or less.

15. The ceramic electronic device of claim 14, wherein the thicknesses of the plurality of internal electrodes are 0.1 m or more and 1 m or less.

16. The ceramic electronic device of claim 1, wherein Sn is solid-solved in a main component ceramic of the plurality of dielectric layers.

17. The ceramic electronic device of claim 1 further comprising an upper cover layer covering the top surface of the multilayer chip.

18. The ceramic electronic device of claim 1 further comprising a lower cover layer covering the bottom surface of the multilayer chip.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 illustrates a perspective view of a multilayer ceramic capacitor in which a cross section of a part of the multilayer ceramic capacitor is illustrated;

[0007] FIG. 2 illustrates a cross sectional view taken along a line A-A of FIG. 1;

[0008] FIG. 3 illustrates a cross sectional view taken along a line B-B of FIG. 1;

[0009] FIG. 4A and FIG. 4B illustrate a Sn concentration;

[0010] FIG. 5 illustrates a Sn concentration;

[0011] FIG. 6 illustrates a manufacturing method of a multilayer ceramic capacitor; and

[0012] FIG. 7A and FIG. 7B illustrate a stacking process.

DETAILED DESCRIPTION

[0013] A metal of the internal electrode layer may diffuse and solid-solved in a main component ceramic of the dielectric layer in a firing process. When the metal of the internal electrode layer is solid-solved in the main component ceramic of the dielectric layer, an oxygen defect is formed in the main component ceramic of the dielectric layer. Insulation characteristic of the dielectric layer is degraded. And, a lifetime of the ceramic electronic devices may be reduced.

[0014] Accordingly, Sn is solid-solved in the main component ceramic of the dielectric layer, solid solution of the main component metal of the internal electrode is suppressed. Insulation characteristic of the dielectric layer is improved. And, the lifetime ca be increased.

[0015] However, Sn promotes sintering of the dielectric layer and promotes spheroidizing of the internal electrode layer. It is therefore possible to improve the insulation characteristic of the dielectric layer by adding Sn. On the other hand, disarrangement of the multilayer structure caused by spheroidizing may decreases an electrostatic capacity.

[0016] A description will be given of an embodiment with reference to the accompanying drawings.

[0017] (Embodiment) FIG. 1 illustrates a perspective view of a multilayer ceramic capacitor 100 in accordance with an embodiment, in which a cross section of a part of the multilayer ceramic capacitor 100 is illustrated. FIG. 2 illustrates a cross sectional view taken along a line A-A of FIG. 1. FIG. 3 illustrates a cross sectional view taken along a line B-B of FIG. 1. As illustrated in FIG. 1 to FIG. 3, the multilayer ceramic capacitor 100 includes a multilayer chip 10 having a rectangular parallelepiped shape, and a pair of external electrodes 20a and 20b that are respectively provided at two end faces of the multilayer chip 10 facing each other. In four faces other than the two end faces of the multilayer chip 10, two faces other than an upper face and a lower face of the multilayer chip 10 in a stacking direction are referred to as side faces. The external electrodes 20a and 20b extend to the upper face, the lower face and the two side faces of the multilayer chip 10. However, the external electrodes 20a and 20b are spaced from each other.

[0018] The multilayer chip 10 has a structure designed to have dielectric layers 11 and internal electrode layers 12 alternately stacked. The dielectric layer 11 includes ceramic material acting as a dielectric material. The internal electrode layers 12 include a base metal material. End edges of the internal electrode layers 12 are alternately exposed to a first end face of the multilayer chip 10 and a second end face of the multilayer chip 10 that is different from the first end face. In the embodiment, the first end face is opposite to the second end face. The external electrode 20a is provided on the first end face. The external electrode 20b is provided on the second end face. Thus, the internal electrode layers 12 are alternately conducted to the external electrode 20a and the external electrode 20b. Thus, the multilayer ceramic capacitor 100 has a structure in which a plurality of dielectric layers 11 are stacked and each two of the dielectric layers 11 sandwich the internal electrode layer 12. In a multilayer structure of the dielectric layers 11 and the internal electrode layers 12, two of the internal electrode layers 12 are positioned at outermost layers in a stacking direction. The upper face and the lower face of the multilayer structure that are the internal electrode layers 12 are covered by cover layers 13. A main component of the cover layer 13 is a ceramic material. For example, a main component of the cover layer 13 is the same as that of the dielectric layer 11.

[0019] For example, the multilayer ceramic capacitor 100 may have a length of 0.25 mm, a width of 0.125 mm and a height of 0.125 mm. The multilayer ceramic capacitor 100 may have a length of 0.4 mm, a width of 0.2 mm and a height of 0.2 mm. The multilayer ceramic capacitor 100 may have a length of 0.6 mm, a width of 0.3 mm and a height of 0.3 mm. The multilayer ceramic capacitor 100 may have a length of 1.0 mm, a width of 0.5 mm and a height of 0.5 mm. The multilayer ceramic capacitor 100 may have a length of 3.2 mm, a width of 1.6 mm and a height of 1.6 mm. The multilayer ceramic capacitor 100 may have a length of 4.5 mm, a width of 3.2 mm and a height of 2.5 mm. However, the size of the multilayer ceramic capacitor 100 is not limited.

[0020] A main component of the internal electrode layers 12 is a base metal such as Ni (nickel), Cu (copper), Sn (tin) or the like. A noble metal such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold) or an alloy thereof may be used as the internal electrode layers 12.

[0021] The dielectric layers 11 are mainly composed of a ceramic material that is expressed by a general formula ABO.sub.3 and has a perovskite structure. The perovskite structure includes ABO.sub.3- having an off-stoichiometric composition. For example, the ceramic material is such as BaTiO.sub.3 (barium titanate), CaZrO.sub.3 (calcium zirconate), CaTiO.sub.3 (calcium titanate), SrTiO.sub.3 (strontium titanate), Ba.sub.1-x-yCa.sub.xSr.sub.yTi.sub.1-zZr.sub.2O.sub.3 (0x1, 0y1, 0z1) having a perovskite structure. An average thickness of each of the dielectric layers 11 may be, for example, 0.05 m or more and 5 m or less. The average thickness may be 0.1 m or more and 3 m or less. The average thickness may be 0.2 m or more and 1 m or less.

[0022] As illustrated in FIG. 2, a section, in which a set of the internal electrode layers 12 connected to the external electrode 20a face another set of the internal electrode layers 12 connected to the external electrode 20b, is a section generating electrical capacity in the multilayer ceramic capacitor 100. Accordingly, the section is referred to as a capacity section 14. That is, the capacity section 14 is a section in which the internal electrode layers next to each other being connected to different external electrodes face each other.

[0023] A section, in which the internal electrode layers 12 connected to the external electrode 20a face each other without sandwiching the internal electrode layer 12 connected to the external electrode 20b, is referred to as an end margin 15. A section, in which the internal electrode layers 12 connected to the external electrode 20b face each other without sandwiching the internal electrode layer 12 connected to the external electrode 20a is another end margin 15. That is, the end margin 15 is a section in which a set of the internal electrode layers 12 connected to one external electrode face each other without sandwiching the internal electrode layer 12 connected to the other external electrode. The end margins 15 are sections that do not generate electrical capacity in the multilayer ceramic capacitor 100.

[0024] As illustrated in FIG. 3, a section of the multilayer chip 10 from the two sides thereof to the internal electrode layers 12 is referred to as a side margin 16. That is, the side margin 16 is a section covering edges of the stacked internal electrode layers 12 in the extension direction toward the two side faces. The side margin 16 does not generate electrical capacity.

[0025] The multilayer chip 10 is obtained by stacking each layer of a powder material and firing the stacked layers. However, there may be a case where the main component metal of the internal electrode layers 12 is solid-solved in the main component ceramic of the dielectric layers 11 during the firing. For example, when the internal electrode layers 12 include Ni, a part of Ni is oxidized during the firing and ionized Ni is solid-solved in the main component ceramic of the dielectric layers 11. When the main component metal of the internal electrode layers 12 is solid-solved in the main component ceramic of the dielectric layers 11, oxygen defects are formed in the main component ceramic of the dielectric layers 11. In this case, the insulation characteristic of the dielectric layers 11 may be degraded and the lifetime of the multilayer ceramic capacitor 100 may be reduced.

[0026] Accordingly, it is thought that Sn is solid-solved in the main component ceramic of the dielectric layers 11. In this case, the solid-solution of the main component metal of the internal electrode layers 12 into the main component ceramic of the dielectric layers 11 is suppressed. The insulation characteristic of the dielectric layers 11 is improved. Therefore, the lifetime of the multilayer ceramic capacitor 100 can be increased.

[0027] However, Sn promotes the sintering of the dielectric layers 11 and promotes spheroidizing of the internal electrode layers 12. Therefore, when Sn is added to the dielectric layers 11, the insulation characteristic of the dielectric layers 11 can be improved. On the other hand, due to disarrangement of the multilayer structure caused by the spheroidizing of the internal electrode layers 12, the electrostatic capacity of the multilayer ceramic capacitor 100 may be reduced. In particular, the heat of a firing furnace is conducted to the multilayer chip before the firing from outside to inside. Therefore, a heat gradient easily occurs. For example, in a high speed temperature increasing of 100 C./min or more, the heat gradient easily becomes remarkable. When the heat gradient occurs, the outside sintering progresses more than the inside sintering. The spheroidizing of the internal electrode layer of outside easily occurs. And, the residual carbon-based material of the binder which prevents the sintering becomes gas from outside to inside and is guided to the atmosphere of the firing furnace. Therefore, the sintering of outside progresses more than the sintering of inside. In particular, the sintering of the outermost internal electrode layer easily becomes remarkable. Accordingly, the multilayer ceramic capacitor 100 of the embodiment has a structure for achieving both the high insulation resistance and the high electrostatic capacity.

[0028] Each of the dielectric layers 11 includes Sn in the multilayer ceramic capacitor 100. For example, Sn is solid-solved in the main component ceramic of each of the dielectric layers 11. Thus, solid solution of the main component metal of the internal electrode layers 12 into the main component ceramic of the dielectric layers 11 during the firing is suppressed. In this case, it is possible to improve the insulation characteristic of the dielectric layers 11. And it is possible to increase the lifetime of the multilayer ceramic capacitor 100. In a relationship among at least two in three or more of the dielectric layers 11, an Sn concentration of one or more of the dielectric layers 11 closer to the end side in the stacking direction is smaller than those of one or more of the dielectric layers 11 on the center side in the stacking direction. The one or more of the dielectric layers 11 on the center side in the stacking direction effectively achieve the improvement of the lifetime. The one or more of the dielectric layers 11 on the end side in the stacking direction suppress the spheroidizing of the internal electrode layers 12. Moreover, the reduction of the continuity modulus is effectively suppressed. The disarrangement of the multilayer structure is suppressed. And, the electrostatic capacity is effectively improved. Accordingly, both the high insulation characteristic and the high electrostatic capacity can be achieved. When the number of the stacked dielectric layers 11 is an even number, center dielectric layers are center two dielectric layers in the stacking direction. When the number of the stacked dielectric layers 11 is an odd number, a center dielectric layer is a center one dielectric layer in a stacking direction.

[0029] For example, as illustrated in FIG. 4A, it is preferable that the Sn concentration of the outermost dielectric layer 11 is the smallest from the center dielectric layer 11 or the center dielectric layers 11 to the outermost dielectric layer 11. In the structure, the suppression of the sintering is remarkable. In FIG. 4A, the outermost dielectric layer 11 in the stacking direction has a black color This means that the Sn concentration of the outermost dielectric layer 11 is the smallest.

[0030] For example, as illustrated in FIG. 4B, it is preferable that the Sn concentrations of a plurality of dielectric layers 11 from the end to the center side in the stacking direction (the dielectric layers 11 in an outer section) are smaller than the Sn concentrations of the rest dielectric layers on the center side in the stacking direction (the dielectric layers in a center section). For example, when 400 numbers of the dielectric layers 11 are stacked, the Sn concentrations of 200 numbers of the dielectric layers 11 in the center of the stacking direction are larger than the Sn concentrations of each 100 numbers of the dielectric layers 11 of the both end sides in the stacking direction. In the structure, the suppression of the sintering is remarkable. In FIG. 4B, the dielectric layers 11 of which the Sn concentration is smaller are illustrated with black.

[0031] When the outer-layer section in which the Sn concentration is law is narrow in FIG. 4B, the effect of the suppression of the sintering may not be necessarily achieved. Accordingly, the range of the outer layer section has a lower limit. For example, it is preferable that the outer layer section is more than 0% from the upper end and the lower end to the center side in the stacking direction within the all dielectric layers 11. It is more preferable that the outer layer section is 5% or more. It is still more preferable that the outer-layer section is 10% or more.

[0032] On the other hand, when the outer layer section in which the Sn concentration is law is wide, the effect of the improvement of the lifetime may not be necessarily achieved. Accordingly, the range of the outer layer section has an upper limit. For example, it is preferable that the outer layer section is more than 40% or less from the upper end and the lower end to the center side in the stacking direction within the all dielectric layers 11. It is more preferable that the outer layer section is 30% or less. It is still more preferable that the outer layer section is 20% or less.

[0033] For example, as illustrated in FIG. 5, it is preferable that the Sn concentrations of the dielectric layers 11 from the center dielectric layer 11 or the center dielectric layers 11 in the stacking direction to the outermost dielectric layers 11 get smaller in steps or gradually from the center internal electrode layer 12 or the center internal electrode layers 12 to the outermost internal electrode layers 12 in the stacking direction. In the structure, the Sn concentrations of the dielectric layers 11 on the end sides of the stacking direction are smaller. Therefore, the suppression of the sintering is remarkable. The Sn concentrations of the dielectric layers 11 on the center side of the stacking direction are larger. Therefore, the improvement of the lifetime is remarkable. When the Sn concentrations gradually get smaller, the Sn concentrations may continuously decrease (monotonous decrease) or the Sn concentrations may repeat up and down and entirely decrease when measuring Sn concentrations at a plurality of sample points from the center dielectric layer 11 or the center dielectric layers 11 in the stacking direction to the outermost dielectric layers 11.

[0034] The thickness of the internal electrode layers 12 may be 0.01 m or more and 5 m or less. The thickness may be 0.05 m or more and 3 m or less. The thickness may be 0.1 m or more and 1 m or less. For example, when the thickness of the internal electrode layers 12 is 1 m or less, the continuity modulus may be reduced because of breaking during the firing. In this case, the effect of the embodiment may be remarkable. In the multilayer ceramic capacitor 100, the number of the internal electrode layers 12 may be 10 to 5000, 50 to 4000, or 100 to 3000.

[0035] When each Sn concentration of the dielectric layers 11 is large, the spheroidizing of the internal electrode layers 12 progresses. In this case, the electrostatic capacity of the multilayer ceramic capacitor 100 may be reduced. Accordingly, it is preferable that each Sn concentration of the dielectric layers 11 has an upper limit. For example, it is preferable that each Sn concentration of the dielectric layers 11 is 5 at % or less. It is more preferable that each Sn concentration is 3 at % or less. It is still more preferable that each Sn concentration is 2 at % or less. The at % of Sn means a ratio of the number of Sn atoms on a presumption that the amount of the main component ceramic is 100 at %. When the main component ceramic of the dielectric layers 11 has the perovskite structure, the at % of Sn means a ratio of the number of Sn atoms on a presumption that the amount of the B site element of the main component ceramic is 100 at %.

[0036] On the other hand, when each Sn concentration of the dielectric layers 11 is small, the diffusion of the metal component of the internal electrode layers 12 into the dielectric layers 11 may not be necessarily suppressed. Accordingly, it is preferable that each Sn concentration of the dielectric layers 11 has a lower limit. For example, it is preferable that each Sn concentration of the dielectric layers 11 is 0.1 at % or more. It is more preferable that each Sn concentration of the dielectric layers 11 is 0.5 at % or more. It is still more preferable that each Sn concentration of the dielectric layers 11 is 1 at % or more.

[0037] For example, in each Sn concentration of the dielectric layers 11, it is preferable that the ratio of the minimum Sn concentration and the maximum Sn concentration is 2:3 or less. It is more preferable that the ratio is 1:3 or less. It is still more preferable that the ratio is 1:5 or less. In each Sn concentration of the dielectric layers 11, it is preferable that a difference between the minimum element ratio of Sn/B site and the maximum element ratio of Sn/B site is 0.001 or more. It is more preferable that the difference is 0.005 or more. It is still more preferable that the difference is 0.01 or more.

[0038] Next, a description will be given of a manufacturing method of the multilayer ceramic capacitor 100. FIG. 6 illustrates a manufacturing method of the multilayer ceramic capacitor 100.

[0039] (Making process of raw material powder) A dielectric material for forming the dielectric layer 11 is prepared. The dielectric material includes the main component ceramic of the dielectric layer 11. Generally, an A site element and a B site element are included in the dielectric layer 11 in a sintered phase of grains of ABO.sub.3. For example, BaTiO.sub.3 is tetragonal compound having a perovskite structure and has a high dielectric constant. Generally, BaTiO.sub.3 is obtained by reacting a titanium material such as titanium dioxide with a barium material such as barium carbonate and synthesizing barium titanate. Various methods can be used as a synthesizing method of the ceramic structuring the dielectric layer 11. For example, a solid-phase method, a sol-gel method, a hydrothermal method or the like can be used. The embodiment may use any of these methods.

[0040] An additive compound may be added to the resulting ceramic powder, in accordance with purposes. The additive compound may be an oxide of tin (Sn), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr) or a rare earth element (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)), or an oxide of cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) and silicon (Si). The additive compound may be a glass including cobalt, nickel, lithium, boron, sodium, potassium or silicon.

[0041] For example, the resulting ceramic raw material powder is wet-blended with additives and is dried and crushed. Thus, a ceramic material is obtained. For example, the grain diameter may be adjusted by crushing the resulting ceramic material as needed. Alternatively, the grain diameter of the resulting ceramic power may be adjusted by combining the crushing and classifying. With the processes, a dielectric material is obtained.

[0042] (Stacking process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the resulting dielectric material and wet-blended. With use of the resulting slurry, a dielectric green sheet 52 is painted on a base material 51 by, for example, a die coater method or a doctor blade method, and then dried. The base material 51 is, for example, PET (polyethylene terephthalate) film.

[0043] Next, as illustrated in FIG. 7A, an internal electrode pattern 53 is formed on the dielectric green sheet 52. In FIG. 7A, as an example, four parts of the internal electrode pattern 53 are formed on the dielectric green sheet 52 and are spaced from each other. The forming method is not limited. For example, electrode paste including NiSn alloy powder or a mixture of Ni powder and Sn powder may be used. A vacuum deposition method such as a sputtering method using a Nu-Sn alloy target may be performed. A simultaneous sputtering using individual targets of Ni and Sn may be performed. The dielectric green sheet 52 on which the internal electrode pattern 53 is formed is a stack unit.

[0044] Next, the dielectric green sheets 52 are peeled from the base materials 51. As illustrated in FIG. 7B, three or more of the stack units are stacked. In this case, the Sn concentration of the dielectric green sheet on the end side is smaller than the Sn concentration of the dielectric green sheet on the center side in the stacking direction, in at least two of the dielectric green sheets. The Sn concentration each dielectric green sheet may be adjusted so that the distribution of the Sn concentration of FIG. 4A to FIG. 5.

[0045] A predetermined number (for example, 2 to 10) of a cover sheet is stacked on an upper face and a lower face of a ceramic multilayer structure of the stacked stack units and is thermally clamped. The resulting ceramic multilayer structure is cut into a chip having a predetermined size (for example, 1.0 mm0.5 mm). In FIG. 7B, the multilayer structure is cut along a dotted line. The components of the cover sheet may be the same as those of the dielectric green sheet 52. Additives of the cover sheet may be different from those of the dielectric green sheet 52.

[0046] (Firing process) The binder is removed from the ceramic multilayer structure in N.sub.2 atmosphere. Metal paste to be the base layers of the external electrodes 20a and 20b is applied to the ceramic multilayer structure by a dipping method. The resulting ceramic multilayer structure is fired for 10 minutes to 2 hours in a reductive atmosphere having an oxygen partial pressure of 10-5 to 10-8 atm in a temperature range of 1100 degrees C. to 1300 degrees C. In this manner, it is possible to manufacture the multilayer ceramic capacitor 100.

[0047] (Re-oxidizing process) After that, a re-oxidizing process may be performed in N.sub.2 gas atmosphere in a temperature range of 600 degrees C. to 1000 degrees C.

[0048] (Plating process) After that, by a plating method, metal layers such as Cu, Ni, Sn or the like may be plated on the external electrodes 20a and 20b.

[0049] In the manufacturing method of the embodiment, in the relationship among at least two layers from the center dielectric layer 11 or the dielectric layers 11 in the stacking direction to the outermost dielectric layer 11, the dielectric layer 11 of which the Sn concentration is smaller is located closer to the end side in the stacking direction than the dielectric layer 11 of which the Sn concentration is larger. Accordingly, both the high insulation characteristic and the high electrostatic capacity of the multilayer ceramic capacitor 100 can be achieved.

[0050] In the embodiments, the multilayer ceramic capacitor is described as an example of ceramic electronic devices. However, the embodiments are not limited to the multilayer ceramic capacitor. For example, the embodiments may be applied to another electronic device such as varistor or thermistor.

Examples

[0051] The multilayer ceramic capacitors in accordance with the embodiment were made and the property was measured.

[0052] (Example 1) An additive was added to barium titanate powder. The additive and the barium titanate powder were sufficiently wet-blended and crushed in a ball mill. Thus, a dielectric material was made. Butyral-based material acting as an organic binder, and toluene and ethanol acting as a solvent were added to the dielectric material. And, the dielectric green sheet was made on a base material of PET by a doctor blade method. Next, an internal electrode pattern was formed on the dielectric green sheet by using paste including Ni powder.

[0053] Next, the dielectric green sheet was peeled from the base material. A plurality of the stack units were stacked. The number of the stack units was 400. Next, a predetermined number of a cover sheet was stacked on an upper face and a lower face of the ceramic multilayer structure of the stacked stack units and was thermally clamped. After that, the resulting ceramic multilayer structure was cut into a chip having a predetermined size (1.0 mm0.5 mm0.5 mm). The added amount of Sn with respect to Ti was 0.50 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 0.25 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section).

[0054] The binder was removed from the ceramic multilayer structure in N.sub.2 atmosphere. Metal paste to be the base layers of the external electrodes was applied to the ceramic multilayer structure by a dipping method. The ceramic multilayer structure was fired in a reductive atmosphere.

[0055] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.004. The atomic concentration ratio of Sn with respect to Ti was 0.001 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section). The vicinity of the center of the chip was cut with use of a slicer. The cut cross section was grinded so that a clean cross section is obtained with use of an ion milling device. The cross section was subjected to a laser ablation ICP mass spectrometry. The amount of elements were measured. Thus, the element concentration ratio of Sn with respect to Ti was measured. The spot diameter of the heating laser was 3 m.

[0056] (Example 2) In an example 2, the added amount of Sn with respect to Ti was 1.00 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 0.50 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). Other conditions were the same as those of the example 1.

[0057] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.009. The atomic concentration ratio of Sn with respect to Ti was 0.004 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0058] (Example 3) In an example 3, the added amount of Sn with respect to Ti was 2.00 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 1.00 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). Other conditions were the same as those of the example 1.

[0059] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.019. The atomic concentration ratio of Sn with respect to Ti was 0.010 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0060] (Example 4) In an example 4, the added amount of Sn with respect to Ti was 2.00 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 1.50 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). Other conditions were the same as those of the example 1.

[0061] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.020. The atomic concentration ratio of Sn with respect to Ti was 0.016 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0062] (Comparative example 1) In a comparative example 1, the added amount of Sn with respect to Ti was 0.00 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 0.00 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). That is, Sn was not added to any of the dielectric green sheets. Other conditions were the same as those of the example 1.

[0063] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.000. The atomic concentration ratio of Sn with respect to Ti was 0.000 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0064] (Comparative example 2) In a comparative example 2, the added amount of Sn with respect to Ti was 0.50 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 1.00 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). Other conditions were the same as those of the example 1.

[0065] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.005. The atomic concentration ratio of Sn with respect to Ti was 0.010 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0066] (Comparative example 3) In a comparative example 3, the added amount of Sn with respect to Ti was 1.00 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 1.00 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). Other conditions were the same as those of the example 1.

[0067] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.009. The atomic concentration ratio of Sn with respect to Ti was 0.010 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0068] (Comparative example 4) In a comparative example 4, the added amount of Sn with respect to Ti was 1.00 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 2.00 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). Other conditions were the same as those of the example 1.

[0069] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.011. The atomic concentration ratio of Sn with respect to Ti was 0.018 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0070] (Comparative example 5) In a comparative example 5, the added amount of Sn with respect to Ti was 2.00 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 2.00 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). Other conditions were the same as those of the example 1.

[0071] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.020. The atomic concentration ratio of Sn with respect to Ti was 0.020 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0072] (Comparative example 6) In a comparative example 6, the added amount of Sn with respect to Ti was 2.00 at % in the 200 numbers of the dielectric green sheets in the center portion in the stacking direction (center section). The added amount of Sn with respect to Ti was 4.00 at % in the 100 numbers of the dielectric green sheets in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric green sheets in the lower portion in the stacking direction (outer layer section). Other conditions were the same as those of the example 1.

[0073] After the firing, the atomic concentration ratio of Sn with respect to Ti in the 200 numbers of dielectric layers in the center portion in the stacking direction (center section) was 0.021. The atomic concentration ratio of Sn with respect to Ti was 0.037 in the 100 numbers of the dielectric layers in the upper portion in the stacking direction (outer layer section) and the 100 numbers of the dielectric layers in the lower portion in the stacking direction (outer layer section).

[0074] A lifetime (50% value) was measured, with respect to each of the examples 1 to 4 and the comparative examples 1 to 6. In the measurement method, a time of each sample, at which the current value exceeds 2 mA when DC 8V was applied in a thermostatic chamber at 120 degrees C., was measured as the lifetime. The lifetime was measured with respect to 100 samples of each of the examples 1 to 4 and the comparative examples 1 to 6.

[0075] An electrostatic capacity was measured with respect to each of the examples 1 to 4 and the comparative examples 1 to 6. In the measurement method, the electrostatic capacity was measured at 120 Hz and 0.5 Vrms with use of an LCR meter. The measurement was performed after 24 hours after returning the temperature to a room temperature after keeping each sample in a thermostatic chamber at 150 degrees C. four 1 hour.

[0076] The continuity modulus of the internal electrode layers in the center section in the stacking direction and the continuity modulus of the internal electrode layers in the outer layer section were measured, with respect each of the examples 1 to 4 and the comparative examples 1 to 6. The vicinity of the center of the chip was cut with use of a slicer. The cut cross section was grinded so that a clean cross section is obtained with use of an ion milling device. The cross section was observed by an SEM. The continuity modulus was measured by dividing a total length of electrodes of each internal electrode layer by the width of the SEM image. Three SEM images of the 5k magnification were captured by shifting positions in the planar direction. n number was 5. An average value of the continuity modulus of 15 SEM images was adopted.

[0077] Table 1 and Table 2 show the measured results. When a lifetime of a sample was improved by 10% or more with respect to the comparative example 1 and a capacity reduction rate of the sample was within 10% with respect to the comparative example 1, the sample was determined as good . The lifetimes of the comparative examples 2 to 6 were longer than that of the comparative example 1. It is thought that this was because Sn was added to the dielectric layers. However, the capacity reduction rates of the comparative examples 2 to 6 were more than 10% with respect to the comparative example 1. Therefore, the comparative examples 2 to 6 were determined as bad x. It is thought that this was because the Sn concentration of the outer layer section was larger than that of the center section, the spheroidizing of the internal electrode layers of the outer layer section progressed, and the disarrangement of the multilayer structure got larger. In contrast, the lifetimes of the examples 1 to 4 were longer than that of the comparative example 1. And, the capacity reduction rates were within 10% with respect to the comparative example 1. Therefore, the examples 1 to 4 were determined as good . It is thought that this was because the Sn concentration of the outer layer section was smaller than that of the center section, and the spheroidizing of the internal electrode layers of the outer layer section was suppressed. The lifetime of the comparative example 1 was not sufficiently long. Therefore, the comparative example 1 was determined as bad x.

TABLE-US-00001 TABLE 1 Sn Sn AMOUNT AMOUNT OF OF OUTER LIFETIME ELECTRO- CENTER LAYER 50% STATIC SECTION SECTION VALUE CAPACITY (at %) (at %) (min) (F) EXAMPLE 1 0.50 0.25 344 4.13 EXAMPLE 2 1.00 0.50 355 4.06 EXAMPLE 3 2.00 1.00 368 3.94 EXAMPLE 4 2.00 1.50 372 3.84 COMPARATIVE 0.00 0.00 312 4.21 EXAMPLE 1 COMPARATIVE 0.50 1.00 353 3.78 EXAMPLE 2 COMPARATIVE 1.00 1.00 362 3.74 EXAMPLE 3 COMPARATIVE 1.00 2.00 370 3.66 EXAMPLE 4 COMPARATIVE 2.00 2.00 375 3.74 EXAMPLE 5 COMPARATIVE 2.00 4.00 370 3.45 EXAMPLE 6

TABLE-US-00002 TABLE 2 CONTINUITY CONTINUITY MODULUS UPPERMOST MODULUS (OUTER CENTER AND (CENTER LAYER SECTION LOWERMOST SECTION) SECTION) DETER- Sn/Ti Sn/Ti (%) (%) MINATION EXAMPLE 1 0.004 0.001 91 95 EXAMPLE 2 0.009 0.004 90 93 EXAMPLE 3 0.019 0.010 89 92 EXAMPLE 4 0.020 0.016 89 90 COMPARATIVE 0.000 0.000 92 96 x EXAMPLE 1 COMPARATIVE 0.005 0.010 91 92 x EXAMPLE 2 COMPARATIVE 0.009 0.010 90 92 x EXAMPLE 3 COMPARATIVE 0.011 0.018 90 90 x EXAMPLE 4 COMPARATIVE 0.020 0.020 89 89 x EXAMPLE 5 COMPARATIVE 0.021 0.037 88 87 x EXAMPLE 6

[0078] Although the embodiments of the present invention have been described in detail, it is to be understood that the various change, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.