Abstract
A transistor includes a substrate having a first surface and a second surface that are opposite to each other. An active layer is disposed on a side of the first surface, and a metal layer is disposed on a side of the second surface. A hole penetrates the substrate and at least a part of the active layer, where in a direction from the substrate to the active layer, the hole includes a first hole segment and a second hole segment, a joint between the first hole segment and the second hole segment has a connection interface, and a hole diameter of the first hole segment is greater than a hole diameter of the second hole segment. A conducting layer is formed on a wall surface of each of the first hole segment and the second hole segment, and the conducting layer is electrically connected to the metal layer.
Claims
1. A transistor, comprising: a substrate, having a first surface and a second surface that are opposite to each other; an active layer and a metal layer, wherein the active layer is disposed on a side of the first surface, and the metal layer is disposed on a side of the second surface; and a hole, wherein the hole passes through the metal layer, the substrate, and at least a part of the active layer, the hole comprises a first hole segment and a second hole segment in a direction from the second surface to the first surface, a joint between the first hole segment and the second hole segment has a connection interface, and a hole diameter of the first hole segment is greater than a hole diameter of the second hole segment, wherein a conducting layer is formed on a wall surface of each of the first hole segment and the second hole segment, and the conducting layer is electrically connected to the metal layer; and the first hole segment and the second hole segment are further filled with a heat dissipation material.
2. The transistor according to claim 1, wherein the heat dissipation material comprises at least one of a silver material and a diamond material.
3. The transistor according to claim 2, wherein the heat dissipation material comprises the silver material and the diamond material, and a mass fraction of the silver material is greater than a mass fraction of the diamond material.
4. The transistor according to claim 1, wherein a step is formed at the joint between the first hole segment and the second hole segment, and the step forms the connection interface.
5. The transistor according to claim 1, wherein a bottom end that is of the first hole segment and that is away from the second surface is located in the substrate.
6. The transistor according to claim 1, wherein in a stacking direction of the substrate and the active layer, a depth of the first hole segment is greater than a depth of the second hole segment.
7. The transistor according to claim 1, wherein in a direction from the first surface to the second surface, the hole diameter of the first hole segment is gradually increased; and/or in the direction from the first surface to the second surface, the hole diameter of the second hole segment is gradually increased.
8. The transistor according to claim 1, wherein the transistor is a field-effect transistor; a source, a gate, and a drain are formed on a side that is of the active layer and that is away from the substrate; and the hole passes through the metal layer, the substrate, and the active layer to the source, and the source is electrically connected to the metal layer through the hole filled with the conducting layer.
9. The transistor according to claim 8, wherein the gate is located between the source and the drain; and an orthographic projection of the first hole segment on the gate covers at least a part of the gate.
10. The transistor according to claim 8, wherein the source extends in a first direction parallel to the substrate; the hole comprises a first hole and a second hole that are separated from each other and arranged in the first direction, and both the first hole and the second hole are filled with the conducting layer and the heat dissipation material; and the same source is electrically connected to the metal layer through the first hole and the second hole.
11. The transistor according to claim 8, wherein the source extends in a first direction parallel to the substrate; a cross section that is of the hole and that is perpendicular to an axial direction of the hole is of a bar-shaped structure extending in the first direction; and the same source is electrically connected to the metal layer through the hole filled with the conducting layer and the heat dissipation material.
12. The transistor according to claim 1, wherein a power of the transistor is greater than or equal to 100 W.
13. A transistor preparation method, comprising: providing a hole that penetrates a substrate and at least a part of an active layer, wherein the substrate has a first surface and a second surface that are opposite to each other, and the active layer is disposed on a side of the first surface; expanding a part that is of the hole and that is close to the second surface to form a first hole segment, wherein a remaining part of the hole is a second hole segment, a hole diameter of the first hole segment is greater than a hole diameter of the second hole segment, and a joint between the first hole segment and the second hole segment has a connection interface; forming a conducting layer on a wall surface of the hole, and forming a metal layer on a side of the second surface, wherein the conducting layer is electrically connected to the metal layer; and filling the first hole segment and the second hole segment with a heat dissipation material.
14. The transistor preparation method according to claim 13, wherein filling the first hole segment and the second hole segment with the heat dissipation material comprises: filling the first hole segment and the second hole segment with sintered silver through dispensing; and curing the sintered silver to form a silver material layer in the first hole segment and the second hole segment.
15. The transistor preparation method according to claim 14, wherein when the first hole segment and the second hole segment are filled with the sintered silver through the dispensing, the sintered silver is doped with diamond.
16. The transistor preparation method according to claim 14, wherein filling the sintered silver through the dispensing comprises: under a negative-pressure condition, enabling the dropped sintered silver to flow into the hole.
17. The transistor preparation method according to claim 13, wherein filling the first hole segment and the second hole segment with the heat dissipation material comprises: forming a diamond seed layer on the conducting layer in a radial direction of the first hole segment and the second hole segment; and forming a diamond layer on the diamond seed layer.
18. The transistor preparation method according to claim 13, wherein a source, a gate, and a drain are formed on a side that is of the active layer and that is away from the substrate, and the source extends in a first direction parallel to the substrate; and providing the hole that penetrates the substrate and at least a part of the active layer comprises: providing a bar-shaped hole extending in the first direction, for the same source to electrically connect to the metal layer through the bar-shaped hole filled with the conducting layer.
19. A semiconductor device package structure, comprising a transistor and a heat dissipation structure; wherein the transistor comprises: a substrate, having a first surface and a second surface that are opposite to each other; an active layer and a metal layer, wherein the active layer is disposed on a side of the first surface, and the metal layer is disposed on a side of the second surface; and a hole, wherein the hole passes through the metal layer, the substrate, and at least a part of the active layer, the hole comprises a first hole segment and a second hole segment in a direction from the second surface to the first surface, a joint between the first hole segment and the second hole segment has a connection interface, and a hole diameter of the first hole segment is greater than a hole diameter of the second hole segment, wherein a conducting layer is formed on a wall surface of each of the first hole segment and the second hole segment, and the conducting layer is electrically connected to the metal layer; and the first hole segment and the second hole segment are further filled with a heat dissipation material; and wherein the heat dissipation structure is disposed on a side of the second surface of the substrate.
20. The semiconductor device package structure according to claim 19, wherein the heat dissipation structure is connected through a silver material layer located between the heat dissipation structure and the metal layer, and the heat dissipation material in the hole is connected to the silver material layer.
Description
BRIEF DESCRIPTION OF DRAWINGS
[0065] FIG. 1 is a diagram of a partial structure of a base station;
[0066] FIG. 2 is a diagram of a package structure of a field-effect transistor according to an embodiment of the present disclosure;
[0067] FIG. 3 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0068] FIG. 4 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0069] FIG. 5 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0070] FIG. 6 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0071] FIG. 7 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0072] FIG. 8A is a diagram of a structure of a hole in a field-effect transistor according to an embodiment of the present disclosure;
[0073] FIG. 8B is a diagram of a structure of a hole in a field-effect transistor in a related technology;
[0074] FIG. 9 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0075] FIG. 10 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0076] FIG. 11 is a diagram of a three-dimensional structure of a field-effect transistor according to an embodiment of the present disclosure;
[0077] FIG. 12 is a diagram of a structure obtained after cutting along M-M in FIG. 11;
[0078] FIG. 13 is an N-direction view of FIG. 11;
[0079] FIG. 14 is a diagram of another structure obtained after cutting along M-M in FIG. 11;
[0080] FIG. 15 is another N-direction view of FIG. 11;
[0081] FIG. 16 is a diagram of a structure including a field-effect transistor according to an embodiment of the present disclosure;
[0082] FIG. 17 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0083] FIG. 18 is a diagram of a structure including a field-effect transistor according to an embodiment of the present disclosure;
[0084] FIG. 19A to FIG. 19I are cross-sectional views of a corresponding process structure after steps in a field-effect transistor manufacturing method are completed according to an embodiment of the present disclosure;
[0085] FIG. 20 is a diagram of a structure of a field-effect transistor according to an embodiment of the present disclosure;
[0086] FIG. 21 is a diagram of a structure including a field-effect transistor according to an embodiment of the present disclosure;
[0087] FIG. 22A is a diagram of a structure of a hole in a field-effect transistor according to an embodiment of the present disclosure;
[0088] FIG. 22B is a diagram of a structure of a hole in a field-effect transistor according to an embodiment of the present disclosure; and
[0089] FIG. 23A to FIG. 23E are cross-sectional views of a corresponding process structure after steps in a field-effect transistor manufacturing method are completed according to an embodiment of the present disclosure.
DESCRIPTION OF EMBODIMENTS
[0090] An embodiment of the present disclosure provides an electronic device. The electronic device may include a communication device (for example, a base station), a wireless charging device, a medical device, a radar, a navigation device, a radio frequency (RF) plasma lighting device, an RF sensing and microwave heating device, and the like. A specific form of the electronic device is not specially limited in embodiments of the present disclosure.
[0091] Reference numerals used in this disclosure include: [0092] 101: field-effect transistor; 102: heat dissipation structure; 103: ceramic frame; 104: cap; [0093] 10: substrate; [0094] 20: active layer; [0095] 201: nucleation layer; [0096] 202: channel layer; [0097] 203: barrier layer; [0098] 301: source; [0099] 302: gate; [0100] 303: drain; [0101] 40: back electrode; [0102] 50: hole; 501: first hole segment; 502: second hole segment; [0103] 50A: first hole; 50B: second hole; [0104] 60: conducting layer; [0105] 70: heat dissipation material; 701: diamond seed layer; 702: diamond layer; [0106] 300: connection layer; [0107] 400: heat dissipation flange; [0108] 500: heat sink; and [0109] 600: air bridge.
[0110] The foregoing electronic device basically includes a semiconductor device, for example, includes a power amplifier (PA). A main function of the PA is to amplify a radio frequency signal. A base station is used as an example. FIG. 1 is a simple diagram of a structure of the base station. The base station includes a control unit, the control unit in the base station includes a radio transceiver, an antenna, a related signal processing circuit, and the like. The control unit mainly includes a cell controller, a voice channel controller, a signaling channel controller, and a multi-channel interface for extension. The control unit of the base station generally controls several base station transceiver stations. Through remote commands of the transceiver stations and mobile stations, the control unit of the base station is used to implement management of all mobile communication interfaces, mainly including radio channel allocation, release, management, and the like.
[0111] Still with reference to FIG. 1, the base station further includes a transmission unit, where the transmission unit is connected to a core network, control signaling on a core network side and voice call or data service information are sent to the control unit of the base station through the transmission unit, and the control unit processes the services.
[0112] With reference to FIG. 1, the base station further includes a baseband unit and a radio frequency (RF) unit. The baseband unit mainly completes functions such as baseband modulation and demodulation, wireless resource allocation, call processing, power control, and soft handover. The RF unit mainly completes conversion between an air radio frequency channel and a baseband digital channel, a power amplifier (A) amplifies a signal, and then the signal is sent to an antenna via a radio frequency feeder for transmission. A terminal device, like a mobile phone or a tablet computer (pad), receives, through a wireless channel, a radio wave transmitted by the antenna, and then obtains, through demodulation, a signal belonging to the terminal device.
[0113] Still with reference to FIG. 1, the base station further includes a power supply unit, where the power supply unit may be configured to supply power to structures such as the transmission unit, the baseband unit, and the control unit.
[0114] In addition, a semiconductor power device is also used in a power charger of a terminal device like a mobile phone, for example, a switch chip in a charger whose power is 60 W, 100 W, 300 W, or the like.
[0115] With development of 4th generation mobile communication technologies (4G) to 5th generation mobile communication technologies (5G), a function requirement for the foregoing semiconductor device is increasingly high, for example, having a higher frequency, a higher voltage, and a higher output power and efficiency.
[0116] Among selectable semiconductor materials, gallium nitride (GaN) becomes a key material for manufacturing a semiconductor device because of its high thermal conductivity, high breakdown field strength, and high saturation electron mobility. For example, a high-electron-mobility transistor (HEMT) based on gallium nitride (GaN) is manufactured by using a GaN epitaxial single-crystal thin film grown on a single-crystal substrate. The single-crystal substrate generally uses a material such as a sapphire (Sapphire), silicon carbide (SiC), or silicon (Si) single crystal. For example, when the substrate uses a silicon single-crystal material, a manufactured HEMT may be referred to as a gallium nitride on silicon (GaN-on-Si) HEMT device.
[0117] A field-effect transistor in the foregoing device may use a package structure shown in FIG. 2, and the package structure may be referred to as a ceramic tube-housing package. Because the field-effect transistor 101 is usually a high-power chip, for example, a chip with high power that may be greater than or equal to 100 W. To ensure working performance of the field-effect transistor, the field-effect transistor 101 is disposed on a heat dissipation structure 102, and the field-effect transistor 101 is connected to a ceramic frame 103 through a lead. Then, the field-effect transistor 101 is led out through gold wire bonding, to be electrically connected to a drive circuit. In addition, the package structure further includes a cap 104, and the field-effect transistor 101 is covered by the cap 104.
[0118] The field-effect transistor 101 shown in FIG. 2 may include a structure shown in FIG. 3 that is an example of a package that may be used with any embodiment. With reference to FIG. 3, FIG. 3 is a sectional view of the field-effect transistor 101 according to an embodiment of the present disclosure. The field-effect transistor 101 includes a substrate 10, and an active layer 20 formed on the substrate 10.
[0119] For example, as shown in FIG. 4, the active layer 20 may include a nucleation layer 201, a channel layer 202 formed on the nucleation layer 201, and a barrier layer 203 formed on the channel layer 202. In other words, film layer structures such as the nucleation layer 201, the channel layer 202, and the barrier layer 203 are sequentially stacked on the substrate 10 in a direction perpendicular to the substrate 10.
[0120] Still with reference to FIG. 4, in the field-effect transistor 101, the nucleation layer 201, the channel layer 202, and the barrier layer 203 may include at least one of aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), and the like.
[0121] For example, the nucleation layer 201 may include an aluminum nitride (AlN) material, aluminum gallium nitride (AlGaN), or the like.
[0122] FIG. 4 merely shows an example of some film layer structures included in the active layer 20 in the field-effect transistor 101. Certainly, more film layer structures may be added based on this embodiment, or some film layer structures may be removed. For example, the active layer 20 may further include a stress buffer layer, an insertion layer, a cap layer, and the like. The stress buffer layer is stacked between the nucleation layer 201 and the channel layer 202, the insertion layer is stacked between the channel layer 202 and the barrier layer 203, and the cap layer is stacked on the barrier layer 203. These active layer structures integrated on the substrate 1 are not specially limited in the present disclosure.
[0123] The field-effect transistor 101 shown in FIG. 3 and FIG. 4 dissipates heat during operation. For example, in a radio frequency GaN HEMT device or a power GaN HEMT device, as a power of the device increases, a temperature increases more obviously, and a junction temperature increases.
[0124] To improve a heat dissipation effect of the device and reduce thermal resistance, as shown in FIG. 3, a hole 50 is provided in the field-effect transistor 101, and the hole 50 penetrates the substrate 10 and at least a part of the active layer 20.
[0125] In addition, the hole 50 is filled with a heat dissipation material. In this way, heat dissipated by the active layer 20 may be conducted to the hole, and the heat is diffused by using the heat dissipation material.
[0126] In some examples, as shown in FIG. 4, the field-effect transistor 101 includes a source 301, a gate 302, and a drain 303. The source 301, the gate 302, and the drain 303 are formed on a side that is of the active layer 20 and that is away from the substrate 10.
[0127] In some scenarios, the gate 302 needs to be electrically connected to a control circuit. For example, as shown in FIG. 2, the field-effect transistor 101 may be electrically connected to the drive circuit through gold wire bonding, to control on and off of the gate 302.
[0128] In some other scenarios, the source 301 may be grounded. For example, a back electrode 40 may be disposed on a side that is of the substrate 10 and that is away from the active layer 20. Further, the hole 50 may sequentially penetrate the substrate 10 and the active layer 20 from the back electrode 40 until the source 301. In addition, a conducting layer 60 may be formed on a wall surface (including a side surface of the hole and a bottom surface of the hole) of the hole 50, and the conducting layer 60 is electrically connected to the back electrode 40. For example, the conducting layer 60 may also be a back electrode, for example, a nickel layer and a gold layer, to implement grounding of the source 301. For example, a thin nickel layer may be first formed on the wall surface of the hole 50, and then a thick gold layer is formed on the nickel layer. This hole 50 may also be referred to as a backside hole, and the back electrode 40 may be referred to as a back electrode.
[0129] In an implementable process, the conducting layer 60 and the back electrode 40 are made of a same material, and may be completed at a time. For example, a layer of nickel may be deposited first, and then a layer of gold material is deposited on the nickel material layer.
[0130] FIG. 4 is an example. In this example, the hole 50 passes through the back electrode 40, the substrate 10, and the active layer 20 until the source 301.
[0131] In another example, the structure shown in FIG. 5 is similar to the structure shown in FIG. 4, and both structures may belong to a GaN HEMT device. The structure shown in FIG. 5 belongs to a GaN HEMT device of an air bridge. In the device, two sources 301 may be electrically connected through an air bridge 600. Similarities between the example shown in FIG. 5 and the example shown in FIG. 4 further include that the conducting layer 60 and a heat dissipation material 70 are filled in the hole 50 for electrically connecting the source 301 to the back electrode 40.
[0132] With reference to FIG. 3 to FIG. 5, it may be understood that in different embodiments provided in the present disclosure, the substrate 10 has a first surface A1 and a second surface A2 that are opposite to each other, the active layer 20 is disposed on a side of the first surface A1, the back electrode 40 is disposed on a side of the second surface A2, and the hole 50 penetrates the back electrode 40, the substrate 10, and at least a part of the active layer 20. The conducting layer 60 in the hole 50 may be used to implement interconnection between a structure on a side of an active surface (a surface having the active layer) of the device and the back electrode 40 on a passive surface (a surface of the substrate).
[0133] In the examples of the present disclosure shown in FIG. 3 to FIG. 5, the heat dissipation material 70 may include at least one of a porous silver material and a diamond material. For example, the heat dissipation material 70 may be a porous silver material. For another example, the heat dissipation material 70 may be a diamond material. For another example, the heat dissipation material 70 may be a mixture of the porous silver material and the diamond material. The diamond material in this embodiment may be understood as at least one of polycrystal diamond and single crystal diamond.
[0134] The hole 50 in this embodiment of the present disclosure has an elongated feature. For example, a depth size of the hole 50 is basically about 100 m or greater than 100 m, and a radial size of the hole 50 may be about 20 m. For example, a size of the hole 50 is 30 m75 m, or a size of the hole is 50 m100 m. For example, a depth size of the hole 50 is twice a radial size.
[0135] During preparation using a process, it is convenient to fill the heat dissipation material 70 into the elongated hole 50. Refer to FIG. 3 to FIG. 5. For the hole 50 in this embodiment of the present disclosure, in a direction from the substrate 10 to the active layer 20 (for example, a direction P in FIG. 3), the hole 50 includes a first hole segment 501 and a second hole segment 502, and a hole diameter size of the first hole segment 501 is greater than a hole diameter size of the second hole segment 502. In this design, the first hole segment 501 that is close to an opening of the hole 50 and that has a large hole diameter is used, so that the heat dissipation material 70 is easily filled in an elongated hole.
[0136] The hole diameter size of the first hole segment 501 and the hole diameter size of the second hole segment 502 in this embodiment of the present disclosure may be understood as a size of the first hole segment 501 in a direction perpendicular to an axial direction of the first hole segment 501, and a size of the second hole segment 502 in a direction perpendicular to an axial direction of the second hole segment 502.
[0137] In some examples, as shown in FIG. 3, in a direction from a second surface A2 to a first surface A1 of the substrate 10, a radial size of the first hole segment 501 is gradually decreased. In some other examples, in a direction from a second surface A2 to a first surface A1 of the substrate 10, a radial size of the second hole segment 502 may also be gradually decreased.
[0138] In some other examples, as shown in FIG. 6, in a direction (for example, a direction P in FIG. 6) from a second surface A2 to a first surface A1 of the substrate 10, a radial size of the first hole segment 501 remains unchanged. In some other examples, in a direction from a second surface A2 to a first surface A1 of the substrate 10, a radial size of the second hole segment 502 may also remain unchanged.
[0139] Still refer to FIG. 6. In this embodiment of the present disclosure, a bottom end of the first hole segment 501 is located in the substrate 10. Certainly, in some implementable structures, the first hole segment 501 with a large hole diameter may also pass through the substrate 10 to the active layer 20.
[0140] As shown in FIG. 6, in a stacking direction of the substrate 10 and the active layer 20, a depth of the first hole segment 501 may be greater than or equal to a depth of the second hole segment 502 (a size in the P direction), or a depth of the first hole segment 501 may be less than a depth of the second hole segment 502. For example, a ratio of the depth of the first hole segment 501 to the depth of the second hole segment 502 may be greater than or equal to 1:1, and less than or equal to 9:1.
[0141] A structure at a joint between the first hole segment 501 and the second hole segment 502 also has a plurality of cases. For example, as shown in FIG. 6, a step is formed at the joint between the first hole segment 501 and the second hole segment 502. For another example, as shown in FIG. 7, no step is formed at the joint between the first hole segment 501 and the second hole segment 502, but the first hole segment 501 and the second hole segment 502 are continuously connected together. Regardless of FIG. 6 or FIG. 7, the joint between the first hole segment 501 and the second hole segment 502 has a connection interface.
[0142] The foregoing merely shows an example in which the hole 50 has one step. In some other examples, a plurality of steps may alternatively be formed because radial sizes of adjacent hole segments are different.
[0143] FIG. 8A and FIG. 8B show holes of two different structures. FIG. 8A shows a hole structure of a same radial size, and FIG. 8B shows a hole structure including the first hole segment 501 with a large hole diameter and the second hole segment 502 with a small hole diameter according to an embodiment of the present disclosure. In this case, when diamond is separately grown in the hole 50 in FIG. 8A and FIG. 8B, a phenomenon of opening closure easily occurs in FIG. 8A, to be specific, an opening at which the diamond is grown is closed, but the interior of the opening is not fully grown with diamond, and a large gap is generated. However, when the hole structure shown in FIG. 8B is used, a phenomenon of opening closure basically does not occur, so that the hole is basically filled with diamond, and a heat dissipation effect is improved.
[0144] As shown in FIG. 9 and FIG. 10, in the field-effect transistor 101 including the active layer 20, the source 301, the gate 302, and the drain 303, a large amount of heat is dissipated from an active region in which the gate 302 is located. To further improve heat dissipation below the gate 302, as shown in FIG. 9 and FIG. 10, an orthographic projection of the hole 50 on the gate 302 needs to cover at least a part of the gate 302. As shown in FIG. 9, a boundary L1 of the first hole segment 501 of the hole 50 may be located within a boundary L2 of the gate 302. Alternatively, as shown in FIG. 10, a hole diameter size of the first hole segment 501 may be increased, so that the opening is in a horn-shaped structure. According to the examples in FIG. 9 and FIG. 10, a heat conduction path below the gate 302 may be shortened, so that the heat is quickly absorbed by the heat dissipation material 70 in the hole 50.
[0145] For example, in the structures shown in FIG. 9 and FIG. 10, the radial size of the first hole segment 501 may be at least twice the radial size of the second hole segment 502, for example, may be twice or three times the radial size of the second hole segment 502. For example, when the radial size of the second hole segment 502 is 20 m, the radial size of the first hole segment 501 may be 50 m.
[0146] Some field-effect transistors 101 may include a plurality of holes 50. For example, as shown in FIG. 11, FIG. 12, and FIG. 13, FIG. 11 shows an example of a diagram of a three-dimensional structure including the substrate 10, the active layer 20, the source 301, the gate 302, the drain 303, and the back electrode 40 that is used as a grounding layer, FIG. 12 is a cross-sectional view obtained after cutting in an M-M direction in FIG. 11, and FIG. 13 is an N-direction view of FIG. 11. With reference to FIG. 11 to FIG. 13, the source 301 extends in a direction parallel to the substrate 10 (for example, in an X direction), and the source 301 is electrically connected to the back electrode 40 through a plurality of holes 50. For example, in FIG. 12 and FIG. 13, it is shown that the plurality of holes 50 include a first hole 50A and a second hole 50B that are separated from each other, and the first hole 50A and the second hole 50B are arranged and are spaced from each other in the X direction. In addition, each hole includes the first hole segment 501 with a large hole diameter and the second hole segment 502 with a small hole diameter.
[0147] FIG. 11 simply shows that one source 301 is electrically connected to the back electrode 40 through two holes 50. In a process structure, both the two holes 50 penetrate the back electrode 40 to the source 301.
[0148] In some other examples, to further improve a heat dissipation effect, FIG. 14 and FIG. 15 show another implementable structure in which the same source 301 is electrically connected to the back electrode 40 through the hole 50, and FIG. 15 is a bottom view of FIG. 14. Through comparison between FIG. 14 and FIG. 12, in FIG. 15, the same source 301 is electrically connected to the back electrode 40 through one hole 50, instead of being electrically connected to the back electrode 40 through a plurality of holes that are separated and spaced from each other. To be specific, in FIG. 14, the first hole 50A and the second hole 50B shown in FIG. 12 may be connected, in other words, a cross section that is of the hole 50 in FIG. 14 and that is perpendicular to an axial direction of the hole 50 extends in a direction consistent with an extension direction of the source 301.
[0149] In this design, on the basis of implementing the electrical connection between the source 301 and the back electrode 40, a wall surface area of the hole 50 may be further increased, so that a filling amount of the heat dissipation material 70 is increased and the heat dissipation effect is improved.
[0150] With reference to FIG. 13 and FIG. 15, in the hole 50 in this embodiment of the present disclosure, a cross section perpendicular to the axial direction of the hole is of an elliptical structure. In this case, hole diameters of the first hole segment 501 and the second hole segment 502 of the hole 50 may be understood as sizes d in minor-axis directions of ellipses shown in FIG. 13 and FIG. 15. In some other embodiments, a cross section that is of the hole 50 and that is perpendicular to the axial direction of the hole may alternatively be of a circular structure. In this case, hole diameters of the first hole segment 501 and the second hole segment 502 of the hole 50 may be understood as a diameter of a circle.
[0151] As shown in FIG. 16, the field-effect transistor 101 may be disposed on a heat dissipation flange (for example, a copper flange is a package flange) 400 through a connection layer 300, and the heat dissipation flange 400 is disposed on a heat sink 500 (which may also be referred to as a tube housing). Some heat dissipated by the field-effect transistor 101 may be conducted to the heat dissipation flange 400 and the heat sink 500 through the connection layer 300, to reduce a device temperature.
[0152] The foregoing provides a description that materials that may be selected for the heat dissipation material 70 provided in the present disclosure may include at least one of a porous silver material and a diamond material. For example, in the field-effect transistor 101 shown in FIG. 16, the heat dissipation material 70 includes the porous silver material. In this case, the connection layer 300 may alternatively be made of a silver material, and the heat dissipation material 70 in the hole 50 may be connected to the silver material used as the connection layer 300.
[0153] In this way, the silver material layer used as the connection layer 300 may also be used as a heat dissipation channel, to improve heat dissipation efficiency of the field-effect transistor 101.
[0154] In the foregoing embodiment, the heat dissipation material 70 may be the porous silver material. In some examples, content of the silver material in the heat dissipation material 70 is 95% to 98%, and the heat dissipation material 70 may be mixed with a substance such as another oxide.
[0155] FIG. 17 is a diagram of a process structure of another field-effect transistor 101 according to an embodiment of the present disclosure. A difference between this embodiment and the foregoing embodiment is that the heat dissipation material 70 not only includes a porous silver material, but also may include diamond, that is, is a mixture of diamond and the porous silver material. For example, the diamond may be single crystal diamond. Because a thermal conductivity of the single crystal diamond is greater than 2000 W/mK, a thermal resistance of the device can be further reduced, and heat dissipation efficiency can be improved.
[0156] In some examples, a mass fraction of the silver material in the heat dissipation material 70 may be greater than a mass fraction of the diamond material. For example, the mass fraction of the diamond material is 20% to 40%, and the mass fraction of the silver material is 60% to 80%.
[0157] FIG. 18 is a diagram of a structure in which the field-effect transistor 101 shown in FIG. 17 is integrated on a heat dissipation flange (for example, a copper flange is a package flange) 400 and the heat dissipation flange 400 is disposed on the heat sink 500. In this implementation structure, the connection layer 300 may alternatively be made of a silver material, and the porous heat dissipation material 70 in the hole 50 may be connected to the silver material used as the connection layer 300. The silver material layer used as the connection layer 300 may also be used as a heat dissipation channel, to improve heat dissipation efficiency of the field-effect transistor 101.
[0158] The following provides a semiconductor device preparation method. In the field-effect transistor 101 prepared by using the method, a heat dissipation material in a hole includes a silver material. A specific preparation process is as follows.
[0159] FIG. 19A to FIG. 19I show a process structure after each step in a process of preparing the field-effect transistor 101 is completed.
[0160] As shown in FIG. 19A, a to-be-processed semiconductor device is provided. A GaN HEMT device is used as an example of the to-be-processed semiconductor device shown in FIG. 19A. The device includes the substrate 10 and the active layer 20 formed on a side of the substrate 10, and the source 301, the gate 302, and the drain 303 that are formed on a side that is of the active layer 20 and that is away from the substrate 10.
[0161] As shown in FIG. 19B, deep hole etching is performed on the substrate 10 (for example, a SiC substrate) of the GaN HEMT device, and an etching depth exceeds a thickness (for example, 50 m to 100 m) of the substrate 10. In addition, a gallium nitride epitaxial layer is etched (that is, the gallium nitride epitaxial layer passes through the active layer 20) to reach the source 301 on the top.
[0162] As shown in FIG. 19C, a step is etched in a surface region of a deep hole of the SiC substrate, and the step makes an inner diameter of a new hole be greater than an original hole diameter. In this way, a hole structure including the first hole segment 501 and the second hole segment 502 shown in FIG. 19C may be formed. For example, when a cross section that is of the first hole segment 501 and that is perpendicular to the axial direction of the hole is elliptical, a size of a major axis that is of the first hole segment and that is close to an opening may be 50 m to 100 m, and a size of a minor axis may be 10 m to 50 m.
[0163] As shown in FIG. 19D, the conducting layer 60 is formed on a wall surface of the hole 50, and the back electrode 40 is formed on a side surface that is of the substrate 10 and that is away from the active layer 20. For example, an Ni material layer may be first formed on a wall surface of the hole 50 and a side surface that is of the substrate 10 and that is away from the active layer 20 through sputtering deposition, and then an Au material layer is formed on the Ni material layer by using an electroplating deposition process, to prepare the back electrode 40 and the conducting layer 60.
[0164] As shown in FIG. 19E and FIG. 19F, dispensing (which may also be referred to as a printing process) of a sintered silver material is performed in the hole 50. A sintered silver adhesive falls on a step and fills in the hole, and under a high-temperature negative-pressure condition, the sintered silver automatically flows into a deep hole and reaches the bottom of the hole. The sintered silver is filled in the hole of the entire device due to repeated dispensing and the negative-pressure condition.
[0165] In some implementable processes, a temperature may range from 50 C. to 150 C. For example, the temperature may range from 70 C. to 80 C. When pressure is less than or equal to 1000 mbar, for example, is 500 mbar to 800 mbar, dispensing of the sintered silver material is performed.
[0166] After the sintered silver fills the hole of the entire device, the sintered silver material in the hole may be cured. For example, sintering is performed at about 200 C., so that the silver material is sintered and cured. The sintered silver material is filled in the hole 50, and as shown in FIG. 19G1, the sintered silver material shrinks to a specific extent due to sintering. In addition, sintered silver of nanoparticles reacts inside a backside hole to form porous silver structure filling shown in FIG. 19G2 and FIG. 19G3.
[0167] As shown in FIG. 19H, dispensing of sintered silver is performed on the heat dissipation flange 400 (for example, a copper flange) for die attaching of the device, and then high-temperature sintering is performed after the dispensing is completed, so that the field-effect transistor 101 and the heat dissipation flange 400 are welded. The sintered silver in the hole 50 is connected to the sintered silver for die attaching to form an effective heat dissipation channel, so as to obtain a structure shown in FIG. 19I.
[0168] In the structure prepared by using the process shown in FIG. 19A to FIG. 19I, under a high-temperature negative-pressure condition, sintered silver may be injected into the hole by using a dispensing process (which may also be referred to as a printing process). In addition, the sintered silver automatically flows into a deep hole and reaches the bottom of the hole. The sintered silver is filled in the hole of the entire device through repeated dispensing and under the high-temperature negative-pressure condition. In this way, a process flow is simple, and no additional process device needs to be further provided.
[0169] In addition, a connection layer is formed on a surface of the heat dissipation flange 400 by using a sintered silver dispensing process, so that the field-effect transistor 101 prepared in FIG. 19H is welded to the heat dissipation flange 400. In this way, sintered silver on the surface of the heat dissipation flange 400 may fill a retracted position of the sintered silver shown in FIG. 19H, and the sintered silver in the hole 50 may be connected to the sintered silver used as the connection layer, to form a heat dissipation channel with a greater area.
[0170] When the process steps shown in FIG. 19E are performed, diamond powder may be mixed in the sintered silver. For example, micrometer-level or nanometer-level diamond powder is evenly distributed inside the sintered silver, to improve overall heat dissipation performance.
[0171] In the different embodiments shown above, the heat dissipation material filled in the hole 50 includes a silver material. FIG. 20 is a diagram of another field-effect transistor 101 filled with different heat dissipation materials according to an embodiment of the present disclosure. The structure shown in FIG. 20 is the same as that in the foregoing embodiment in that the structure includes the hole 50 that penetrates the back electrode 40, the substrate 10, and the active layer 20, and a wall surface of the hole 50 is covered with the conducting layer 60. In the structure shown in FIG. 20, the heat dissipation material 70 is single crystal diamond or polycrystal diamond. For example, a thermal conductivity of the polycrystal diamond is usually greater than 1400 W/mK, so that a heat dissipation effect can be significantly improved, and a highest junction temperature of the device can be reduced.
[0172] As shown in FIG. 21, the field-effect transistor 101 may be disposed on the heat dissipation flange 400 through the connection layer 300, and the heat dissipation flange 400 is disposed on the heat sink 500. The connection layer 300 may be a silver material layer made of sintered silver.
[0173] The following Table 1 shows highest temperatures of layers when different heat dissipation materials are used in the structure shown in FIG. 21.
TABLE-US-00001 TABLE 1 Highest temperature No Silver of each layer filling material Diamond GaN layer 118.5 C. 113.1 C. 103.1 C. SiC substrate 115.8 C. 110.3 C. 101.7 C. Connection layer 97.2 C. 96.5 C. 95.8 C. Heat dissipation flange 90.9 C. 90.9 C. 90.7 C.
[0174] Based on the data in Table 1, it can be learned that when the hole 50 is not filled with the heat dissipation material, a highest temperature of the GaN layer is obviously higher than that of the GaN layer in which the heat dissipation material including the silver material and the diamond is filled. Therefore, when the silver material or the diamond material provided in this embodiment of the present disclosure is used, a highest temperature of each layer structure can be significantly reduced, thermal resistance of the device can be reduced, and a heat dissipation effect can be improved.
[0175] In the structure shown in FIG. 21, when the hole 50 uses two different structures in FIG. 22A and FIG. 22B and uses different heat dissipation materials, the following Table 2 shows impact on a highest junction temperature of the device. In addition, in this example, major axes of the first hole 50A and the second hole 50B whose cross sections are elliptical in FIG. 22A have major axis sizes of 50 m to 100 m, and minor axis sizes of 10 m to 50 m. The hole 50 whose cross section is elliptical in FIG. 22B has a major axis size of 100 m to 400 m, and a minor axis size of 10 m to 50 m.
TABLE-US-00002 TABLE 2 No filling Silver material Diamond Example 1 0 6.9% 19% Example 2 0 11.3% 31.9%
[0176] Example 1 in Table 2 shows a heat gain of the device when the same source 301 is electrically connected to the back electrode through the separated hole 50 in FIG. 22A, and the silver material or the diamond material is used. For example, when the silver material is used as the heat dissipation material, the heat gain reaches (90.9/113.1)%=6.9%.
[0177] Example 2 in Table 2 shows a heat gain of the device when the same source 301 is electrically connected to the back electrode through the hole 50 in FIG. 22B and the silver material or the diamond material is used. For example, when the silver material is used as the heat dissipation material, the heat gain reaches 11.3%.
[0178] It can be learned from the data in Table 2 that, regardless of whether Example 1 or Example 2 is used, filling the hole with the silver material and the diamond material significantly reduces a temperature of the device in comparison with not filling the hole with any heat dissipation material.
[0179] The following provides a semiconductor device preparation method. In the field-effect transistor 101 prepared by using the method, a heat dissipation material in a hole includes diamond. A specific preparation process is as follows.
[0180] FIG. 23A to FIG. 23E show a process structure after each step in a process of preparing the field-effect transistor 101 is completed. In FIG. 23A to FIG. 23E, a GaN HEMT device is used as an example to describe a preparation process.
[0181] As shown in FIG. 23A, deep hole etching is performed on the substrate 10 (for example, a SiC substrate) of the GaN HEMT device, and an etching depth exceeds a thickness (for example, 50 m to 100 m) of the substrate 10. In addition, a gallium nitride epitaxial layer is etched (that is, the gallium nitride epitaxial layer passes through the active layer 20) to reach the source 301 on the top.
[0182] As shown in FIG. 23B, a step is etched in a surface region of a deep hole of the SiC substrate. In this way, a hole structure that includes the first hole segment 501 and the second hole segment 502 and that is shown in FIG. 23B may be formed. In FIG. 23B, there is no step at a joint between the first hole segment 501 and the second hole segment 502.
[0183] As shown in FIG. 23C, the conducting layer 60 is formed on a wall surface of the hole 50, and the back electrode 40 is formed on a side surface that is of the substrate 10 and that is away from the active layer 20.
[0184] As shown in FIG. 23D, a diamond seed layer 701 is grown on the conducting layer 60 in the hole 50.
[0185] As shown in FIG. 23E, a single crystal or polycrystal diamond layer 702 is grown on the diamond seed layer 701 to fill the hole. For example, the polycrystal diamond layer 702 may be grown on the diamond seed layer 702, to reduce growth difficulty of the diamond seed layer 702.
[0186] In the semiconductor device prepared as shown in FIG. 23A to FIG. 23E, a heat gain of the device may be more than 19%, and a highest junction temperature of the device is significantly reduced.
[0187] Based on the foregoing two methods for preparing different semiconductor devices, it may be considered that the following process method may be roughly used in an implementable process.
[0188] S1: Provide a hole that penetrates a substrate and an active layer to a front electrode, where the substrate has a first surface and a second surface that are opposite to each other, the active layer is disposed on a side of the first surface, and the front electrode is disposed on a side that is of the active layer and that is away from the substrate.
[0189] S2: Expand a part that is of the hole and that is close to the second surface to form a first hole segment, where a remaining part of the hole is a second hole segment, a hole diameter of the first hole segment is greater than a hole diameter of the second hole segment, and a step is formed at a joint between the first hole segment and the second hole segment.
[0190] S3: Form a conducting layer on a wall surface of the hole, and form a back electrode on a side of the second surface, where the conducting layer is electrically connected to the back electrode. For example, when a HEMT device based on GaN is used, the back electrode is located at a ground layer to which the source is electrically connected.
[0191] S4: Fill the first hole segment and the second hole segment with a heat dissipation material, where the heat dissipation material includes at least one of a silver material and a diamond material. For example, sintered silver may be injected by using a dispensing process, or a diamond layer may be formed by using an epitaxial growth process.
[0192] In the descriptions of this specification, the described specific features, structures, materials, or characteristics may be combined in a proper manner in any one or more of embodiments or examples.
[0193] The foregoing descriptions are merely specific implementations of the present disclosure, but are not intended to limit the protection scope of the present disclosure. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present disclosure shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
