Error control in memory systems using combinational circuits

Abstract

In some implementations, a memory system may obtain, from a host system, a command to read data. The memory system may retrieve a codeword associated with the data. The memory system may generate, based on the codeword, a syndrome. The memory system may generate one or more decoding values based on the syndrome and using one or more combinational circuits. The memory system may correct one or more errors in the codeword using the one or more decoding values. The memory system may provide the data to the host system.

Claims

1. A memory apparatus, comprising: a syndrome generator configured to generate a syndrome based on a codeword; a decoding value generator coupled to the syndrome generator, the decoding value generator configured to generate one or more decoding values based on the syndrome and using one or more combinational circuits; and an error value generator configured to generate an error value associated with the codeword based on the one or more decoding values, wherein, to generate the error value, the error value generator is configured to identify, using a mapping between one or more elements of an algebraic field and one or more inverse elements of the algebraic field, an inverse of a decoding value of the one or more decoding values.

2. The memory apparatus of claim 1, wherein each combinational circuit of the one or more combinational circuits is configured to obtain a respective subset of one or more syndrome values of the syndrome and configured to output a respective decoding value of the one or more decoding values.

3. The memory apparatus of claim 1, further comprising: an error position generator coupled to the decoding value generator, the error position generator configured to obtain a subset of the one or more decoding values and generate, using a second one or more combinational circuits, one or more values indicating a position of the error value.

4. The memory apparatus of claim 3, further comprising: a flag generator coupled to the syndrome generator, the decoding value generator, and the error position generator, wherein the flag generator is configured to identify whether the codeword includes one or more errors.

5. The memory apparatus of claim 3, further comprising: one or more coefficient generators coupled to the decoding value generator, each coefficient generator configured to obtain a respective decoding value of the one or more decoding values and provide a respective set of coefficients of the respective decoding value to the error position generator.

6. The memory apparatus of claim 1, further comprising: an encoder configured to generate the codeword using a second one or more combinational circuits and data associated with a write command, wherein the codeword includes the data.

7. The memory apparatus of claim 1, wherein, to generate the error value, the error value generator is configured to: calculate, using a second one or more combinational circuits, the inverse of the decoding value of the one or more decoding values.

8. A method, comprising: obtaining, by a memory system and from a host system, a command to read data; retrieving, by the memory system, a codeword associated with the data; generating, by the memory system and based on the codeword, a syndrome; generating, by the memory system, one or more decoding values based on the syndrome and using one or more combinational circuits; correcting, by the memory system, one or more errors in the codeword using the one or more decoding values, wherein correcting the one or more errors comprises identifying, using a mapping between one or more elements of an algebraic field and one or more inverse elements of the algebraic field, an inverse of a decoding value of the one or more decoding values; and providing the data to the host system.

9. The method of claim 8, wherein correcting the one or more errors further comprises: obtaining, at an error value generator, a subset of the one or more decoding values; generating an error value using the subset of the one or more decoding values; and adding the error value to the codeword to correct the one or more errors.

10. The method of claim 9, wherein generating the error value comprises: calculating, using a second one or more combinational circuits, the inverse of the decoding value.

11. The method of claim 8, further comprising: generating, at a flag generator coupled to a decoding value generator, one or more values indicating whether the codeword includes the one or more errors.

12. The method of claim 8, further comprising: obtaining, from the host system, a second command to store the data; generating, at an encoder and using a second one or more combinational circuits, first parity information, wherein the codeword includes the first parity information and the data; and storing the codeword to one or more memory arrays of the memory system.

13. The method of claim 12, further comprising: generating, using a cyclic redundancy check (CRC) operation, second parity information, wherein the codeword further includes the second parity information.

14. The method of claim 8, further comprising: storing, at a buffer of the memory system, the syndrome, wherein generating the one or more decoding values comprises obtaining the syndrome from the buffer.

15. The method of claim 8, further comprising: storing, at a buffer of the memory system, the one or more decoding values, wherein correcting the one or more errors comprises obtaining the one or more decoding values from the buffer.

16. A method, further comprising: obtaining, by a memory system and from a host system, a command to read data; generating, by the memory system and using one or more combinational circuits, one or more decoding values based on a syndrome associated with a codeword that is associated with the data; obtaining, at an error position generator coupled to a decoding value generator, a first subset of the one or more decoding values; generating, using a second one or more combinational circuits of the error position generator, one or more values indicating a position of an error value; providing the one or more values to an error value generator; generating, at the error value generator, the error value using a second subset of the one or more decoding values; adding, by the memory system, the error value to the codeword to correct one or more errors in the codeword; and providing the data to the host system.

17. The method of claim 16, further comprising: generating, using one or more coefficient generators, respective sets of coefficients of the second subset of decoding values, wherein generating the one or more values is based on the respective sets of coefficients.

18. The method of claim 16, wherein generating the error value further comprises: calculating, using a third one or more combinational circuits, an inverse of a decoding value of the one or more decoding values.

19. The method of claim 16, further comprising: generating, at a flag generator coupled to the decoding value generator, one or more values indicating whether the codeword includes the one or more errors.

20. The method of claim 16, further comprising: obtaining, from the host system, a second command to store the data; generating, at an encoder and using a third one or more combinational circuits, first parity information, wherein the codeword includes the first parity information and the data; and storing the codeword to one or more memory arrays of the memory system.

21. A memory apparatus, comprising: one or more controllers configured to: obtain, from a host system, a command to read data; retrieve a codeword associated with the data; generate, at a syndrome generator of the memory apparatus and based on the codeword, a syndrome; generate, at a decoding value generator of the memory apparatus, one or more decoding values based on the syndrome and using one or more combinational circuits; correct one or more errors in the codeword using the one or more decoding values, wherein, to correct the one or more errors, the one or more controllers are configured to identify, using a mapping between one or more elements of an algebraic field and one or more inverse elements of the algebraic field, an inverse of a decoding value of the one or more decoding values; and provide the data to the host system.

22. The memory apparatus of claim 21, wherein, to correct the one or more errors, the one or more controllers are further configured to: obtain, at an error value generator, a subset of the one or more decoding values; generate an error value using the subset of the one or more decoding values; and add the error value to the codeword to correct the one or more errors.

23. The memory apparatus of claim 22, wherein, to generate the error value, the one or more controllers are further configured to: calculate, using a second one or more combinational circuits, an inverse of a decoding value of the one or more decoding values.

24. The memory apparatus of claim 22, wherein the one or more controllers are further configured to: obtain, at an error position generator coupled to the decoding value generator, a second subset of the one or more decoding values; generate, using a second one or more combinational circuits of the error position generator, one or more values indicating a position of the error value; and provide the one or more values to the error value generator, wherein generating the error value is based on the one or more values.

25. The memory apparatus of claim 24, wherein the one or more controllers are further configured to: generate, using one or more coefficient generators, respective sets of coefficients of the second subset of decoding values, wherein generating the one or more values is based on the respective sets of coefficients.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram illustrating an example system capable of error control in memory systems using combinational circuits.

(2) FIG. 2 is a diagram illustrating an example of a system capable of error control in memory systems using combinational circuits.

(3) FIG. 3 is a diagram illustrating an example of a data structure capable of error control in memory systems using combinational circuits.

(4) FIG. 4 is a diagram illustrating an example of an encoder capable of error control in memory systems using combinational circuits.

(5) FIG. 5 is a diagram illustrating an example of a system that supports error control in memory systems using combinational circuits.

(6) FIG. 6 is a diagram illustrating an example of a system that supports error control in memory systems using combinational circuits.

(7) FIG. 7 is a diagram illustrating an example of a system that supports error control in memory systems using combinational circuits.

(8) FIG. 8 is a diagram illustrating an example of a system that supports error control in memory systems using combinational circuits.

(9) FIG. 9 is a flowchart of an example method associated with error control in memory systems using combinational circuits.

DETAILED DESCRIPTION

(10) Memory systems may use multiple data protection mechanisms, such as chipkill (CK) schemes in which data and parity information associated with the data may be stored across multiple locations (e.g., stored across multiple blocks, multiple planes, and/or multiple memory dies), as well as non-chipkill (NOCK) schemes in which data and parity information may be stored to a continuous range of addresses (e.g., a continuous range of physical addresses and/or a continuous range of logical addresses). In some cases, NOCK schemes may include error control operations capable of correcting up to two errors in a unit of data. For example, a memory system may communicate data (e.g., may obtain data from a host system, may write data, and may read data) as one or more data packets, in which each data packet includes 64 symbols. As described herein a symbol refers to an 8-bit sequence of data (e.g., a byte). However, techniques described herein may apply to symbols of other sizes. A NOCK error control scheme for such a memory system may support correcting up to two symbols in the data packet (e.g., the error control scheme may use a double symbol correcting (DSC) code).

(11) Some memory systems may implement such DSC codes using iterative logic. For example, to correct one or more errors in a data packet, a memory system may identify an error locator polynomial and iteratively identify one or more roots of the error locator polynomial. The memory system may then use the one or more roots to identify one or more error values using an error evaluator polynomial. However, such an iterative algorithm may implement one or more sequential circuits. As described herein, a sequential circuit is a circuit having an output that, for a given time, is dependent on one or more inputs at the given time, as well as previous inputs to the circuit (e.g., the output of the circuit may depend on inputs prior to the given time). Thus, such iterative algorithms may be resource intensive (e.g., may use a large amount of processing resources and/or energy resources), and may use relatively complicated processing circuitry, which may reduce the performance of the memory system, may increase the power consumption of the memory system, and/or may limit the accuracy of error correction schemes.

(12) Some implementations described herein enable error control in memory systems using combinational logic. For example, to encode a data packet according to a DSC error correction scheme, the memory system may generate parity information for the data packet using a first one or more combinational circuits. As described herein, a combinational circuit is a circuit having an output that, for a given time, is dependent on one or more inputs at the given time, regardless of previous inputs to the circuit (e.g., regardless of inputs prior to the given time). For example, a combinational circuit may include one or more adder circuits configured to obtain a set of inputs and output the sum of the inputs, one or more subtractor circuits configured to obtain a set of inputs and output a difference of the inputs, one or more exclusive-or (XOR) circuits to obtain a set of inputs and output the result of an XOR operation of the inputs, one or more multiplexers, and/or one or more demultiplexers, among other examples. Because the output of a combinational circuit depends on current inputs, rather than a combination of current and previous inputs, the performance of combinational circuits may be greater than other types of circuits, such as sequential circuits in which an output depends on both the current inputs and previous inputs. For example, a sequence of combinational circuits may obtain one or more inputs and generate one or more outputs in a reduced quantity of clock cycles (e.g., a single clock cycle), as compared with a sequence of sequential circuits.

(13) To decode the data packet according to the DSC error correction scheme, the memory system may generate one or more syndrome values using a second one or more combinational circuits. The memory system may provide the one or more syndrome values to a third one or more combinational circuits to generate one or more decoding values. The one or more decoding values may indicate information associated with one or more errors in the data packet. For example, the memory system may provide a first subset of the one or more decoding values to a fourth one or more combinational circuits to generate one or more error position values. The memory system may provide a second subset of the one or more decoding values to a fifth one or more combinational circuits to generate one or more error values. The memory system may use the one or more error values to correct one or more errors in the data packet.

(14) As a result, by enabling error control in memory systems using combinational logic, the memory system may enable encoding and/or decoding a data packet using the DSC error correction scheme. For example, by encoding a data packet using one or more combinational circuits, the memory system may enable generating parity information for the DSC error scheme while reducing reliance on sequential circuits. Additionally, by generating the decoding values using one or more combinational circuits, the memory system may enable decoding the data packet while reducing reliance on sequential circuits. Said another way, the one or more combinational circuits may enable a fully-algebraic implementation of the DSC error correction scheme. Such an implementation may improve the performance of encoding and/or decoding a data packet, such as by reducing the quantity of resources (e.g., processing resources and/or energy resources) used to encode and/or decode the data packet, may increase the speed at which the data packet is encoded and/or decoded, and may reduce the complexity of processing circuitry used to encode and/or decode the data packet.

(15) FIG. 1 is a diagram illustrating an example system 100 capable of error control in memory systems using combinational circuits. The system 100 may include one or more devices, apparatuses, and/or components for performing operations described herein. For example, the system 100 may include a host system 105 and a memory system 110. The memory system 110 may include a memory system controller 115 and one or more memory devices 120, shown as memory devices 120-1 through 120-N (where N1). A memory device may include a local controller 125 and one or more memory arrays 130. The host system 105 may communicate with the memory system 110 (e.g., the memory system controller 115 of the memory system 110) via a host interface 140. The memory system controller 115 and the memory devices 120 may communicate via respective memory interfaces 145, shown as memory interfaces 145-1 through 145-N (where N1).

(16) The system 100 may be any electronic device configured to store data in memory. For example, the system 100 may be a computer, a mobile phone, a wired or wireless communication device, a network device, a server, a device in a data center, a device in a cloud computing environment, a vehicle (e.g., an automobile or an airplane), and/or an Internet of Things (IoT) device. The host system 105 may include a host processor 150. The host processor 150 may include one or more processors configured to execute instructions and store data in the memory system 110. For example, the host processor 150 may include a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and/or another type of processing component.

(17) The memory system 110 may be any electronic device or apparatus configured to store data in memory. For example, the memory system 110 may be a hard drive, a solid-state drive (SSD), a flash memory system (e.g., a NAND flash memory system or a NOR flash memory system), a universal serial bus (USB) drive, a memory card (e.g., a secure digital (SD) card), a secondary storage device, a non-volatile memory express (NVMe) device, an embedded multimedia card (eMMC) device, a dual in-line memory module (DIMM), and/or a random-access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device.

(18) The memory system controller 115 may be any device configured to control operations of the memory system 110 and/or operations of the memory devices 120. For example, the memory system controller 115 may include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and/or one or more processing components. In some implementations, the memory system controller 115 may communicate with the host system 105 and may instruct one or more memory devices 120 regarding memory operations to be performed by those one or more memory devices 120 based on one or more instructions from the host system 105. For example, the memory system controller 115 may provide instructions to a local controller 125 regarding memory operations to be performed by the local controller 125 in connection with a corresponding memory device 120.

(19) A memory device 120 may include a local controller 125 and one or more memory arrays 130. In some implementations, a memory device 120 includes a single memory array 130. In some implementations, each memory device 120 of the memory system 110 may be implemented in a separate semiconductor package or on a separate die that includes a respective local controller 125 and a respective memory array 130 of that memory device 120. The memory system 110 may include multiple memory devices 120.

(20) A local controller 125 may be any device configured to control memory operations of a memory device 120 within which the local controller 125 is included (e.g., and not to control memory operations of other memory devices 120). For example, the local controller 125 may include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and/or one or more processing components. In some implementations, the local controller 125 may communicate with the memory system controller 115 and may control operations performed on a memory array 130 coupled with the local controller 125 based on one or more instructions from the memory system controller 115. As an example, the memory system controller 115 may be an SSD controller, and the local controller 125 may be a NAND controller.

(21) A memory array 130 may include an array of memory cells configured to store data. For example, a memory array 130 may include a non-volatile memory array (e.g., a NAND memory array or a NOR memory array) or a volatile memory array (e.g., an SRAM array or a DRAM array). In some implementations, the memory system 110 may include one or more volatile memory arrays 135. A volatile memory array 135 may include an SRAM array and/or a DRAM array, among other examples. The one or more volatile memory arrays 135 may be included in the memory system controller 115, in one or more memory devices 120, and/or in both the memory system controller 115 and one or more memory devices 120. In some implementations, the memory system 110 may include both non-volatile memory capable of maintaining stored data after the memory system 110 is powered off and volatile memory (e.g., a volatile memory array 135) that requires power to maintain stored data and that loses stored data after the memory system 110 is powered off. For example, a volatile memory array 135 may cache data read from or to be written to non-volatile memory, and/or may cache instructions to be executed by a controller of the memory system 110.

(22) The host interface 140 enables communication between the host system 105 (e.g., the host processor 150) and the memory system 110 (e.g., the memory system controller 115). The host interface 140 may include, for example, a Small Computer System Interface (SCSI), a Serial-Attached SCSI (SAS), a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, an NVMe interface, a USB interface, a Universal Flash Storage (UFS) interface, an eMMC interface, a double data rate (DDR) interface, and/or a DIMM interface.

(23) The memory interface 145 enables communication between the memory system 110 and the memory device 120. The memory interface 145 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Additionally, or alternatively, the memory interface 145 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a DDR interface.

(24) Although the example memory system 110 described above includes a memory system controller 115, in some implementations, the memory system 110 does not include a memory system controller 115. For example, an external controller (e.g., included in the host system 105) and/or one or more local controllers 125 included in one or more corresponding memory devices 120 may perform the operations described herein as being performed by the memory system controller 115. Furthermore, as used herein, a controller may refer to the memory system controller 115, a local controller 125, or an external controller. In some implementations, a set of operations described herein as being performed by a controller may be performed by a single controller. For example, the entire set of operations may be performed by a single memory system controller 115, a single local controller 125, or a single external controller. Alternatively, a set of operations described herein as being performed by a controller may be performed by more than one controller. For example, a first subset of the operations may be performed by the memory system controller 115 and a second subset of the operations may be performed by a local controller 125. Furthermore, the term memory apparatus may refer to the memory system 110 or a memory device 120, depending on the context.

(25) A controller (e.g., the memory system controller 115, a local controller 125, or an external controller) may control operations performed on memory (e.g., a memory array 130), such as by executing one or more instructions. For example, the memory system 110 and/or a memory device 120 may store one or more instructions in memory as firmware, and the controller may execute those one or more instructions. Additionally, or alternatively, the controller may receive one or more instructions from the host system 105 and/or from the memory system controller 115, and may execute those one or more instructions. In some implementations, a non-transitory computer-readable medium (e.g., volatile memory and/or non-volatile memory) may store a set of instructions (e.g., one or more instructions or code) for execution by the controller. The controller may execute the set of instructions to perform one or more operations or methods described herein. In some implementations, execution of the set of instructions, by the controller, causes the controller, the memory system 110, and/or a memory device 120 to perform one or more operations or methods described herein. In some implementations, hardwired circuitry is used instead of or in combination with the one or more instructions to perform one or more operations or methods described herein. Additionally, or alternatively, the controller may be configured to perform one or more operations or methods described herein. An instruction is sometimes called a command.

(26) For example, the controller (e.g., the memory system controller 115, a local controller 125, or an external controller) may transmit signals to and/or receive signals from memory (e.g., one or more memory arrays 130) based on the one or more instructions, such as to transfer data to (e.g., write or program), to transfer data from (e.g., read), to erase, and/or to refresh all or a portion of the memory (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of the memory). Additionally, or alternatively, the controller may be configured to control access to the memory and/or to provide a translation layer between the host system 105 and the memory (e.g., for mapping logical addresses to physical addresses of a memory array 130). In some implementations, the controller may translate a host interface command (e.g., a command received from the host system 105) into a memory interface command (e.g., a command for performing an operation on a memory array 130).

(27) In some implementations, one or more systems, devices, apparatuses, components, and/or controllers of FIG. 1 may include: a syndrome generator configured to generate a syndrome based on a codeword; a decoding value generator coupled to the syndrome generator, the decoding value generator configured to generate one or more decoding values based on the syndrome and using one or more combinational circuits; and an error value generator configured to generate an error value associated with the codeword based on the one or more decoding values.

(28) In some implementations, one or more systems, devices, apparatuses, components, and/or controllers of FIG. 1 may be configured to: obtain, from a host system, a command to read data; retrieve a codeword associated with the data; generate, based on the codeword, a syndrome; generate one or more decoding values based on the syndrome and using one or more combinational circuits; correct one or more errors in the codeword using the one or more decoding values; and provide the data to the host system.

(29) In some implementations, one or more systems, devices, apparatuses, components, and/or controllers of FIG. 1 may be configured to: obtain, from a host system, a command to read data; retrieve a codeword associated with the data; generate, at a syndrome generator and based on the codeword, a syndrome; generate, at a decoding value generator, one or more decoding values based on the syndrome and using one or more combinational circuits; correct one or more errors in the codeword using the one or more decoding values; and provide the data to the host system.

(30) The number and arrangement of components shown in FIG. 1 are provided as an example. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in FIG. 1. Furthermore, two or more components shown in FIG. 1 may be implemented within a single component, or a single component shown in FIG. 1 may be implemented as multiple, distributed components. Additionally, or alternatively, a set of components (e.g., one or more components) shown in FIG. 1 may perform one or more operations described as being performed by another set of components shown in FIG. 1.

(31) FIG. 2 is a diagram illustrating an example of a system 200 capable of error control in memory systems using combinational circuits. The system 200 may include one or more data paths, such as a write data path 205 and a read data path 210 of one or more devices, apparatuses, and/or components for performing operations described herein. For example, the memory system may store data to one or more memory arrays 215 (e.g., memory arrays 130) via the write data path 205. Further, the memory system may retrieve data from the one or more memory arrays 215 via the read data path 210. In some implementations, the system 200 may be implemented in a compute express link (CXL) system. For example, the system 200 may be implemented within a memory system (e.g., the memory system 110) that includes a CXL controller and one or more memory devices 120.

(32) The memory system may implement one or more data protection schemes to increase the reliability of data stored to the one or more memory arrays 215. For example, as part of storing a data packet 220 to the one or more memory arrays 215, the memory system may generate one or more codewords, such as a codeword 225 and a codeword 230, using respective data protection schemes. The data packet 220 may include data obtained from a host system (e.g., the host system 105), and may be organized into one or more symbols. In some implementations, a data packet 220 may include a given quantity of symbols, such as 64 symbols, and a symbol may include a given quantity of data, such as eight bits. Accordingly, a data packet 220 may include 64 bytes.

(33) In some examples, the memory system may obtain, from the host system, a command to store a data packet 220 to the one or more memory arrays 215 (e.g., a write command). To store a data packet 220, the memory system may generate a codeword 225 using an encoder 235. The encoder 235 may be configured to calculate first parity information using the data packet 220. The encoder 235 may combine the first parity information with the data packet 220 to generate the codeword 225, such as by appending the first parity information to the data packet 220. In some implementations, the first parity information may be cyclic redundancy check (CRC) value. The first parity information may include a given quantity of data, such as 32 bits (e.g., four symbols). Accordingly, the codeword 225 may include 68 symbols (e.g., 68 bytes). Additionally, the memory system may generate a codeword 230 using an encoder 240. The encoder 240 may be configured to calculate second parity information using the data packet 220 and using one or more combinational circuits, as described in greater detail in connection to FIG. 4. The encoder 240 may combine the second parity information with the codeword 225 to generate the codeword 230, such as by appending the second parity information to the codeword 230.

(34) The second parity information may be configured to correct up to two corrupted symbols in the data packet 220 and/or the codeword 225. As described herein, a corrupted symbol is a symbol in which one or more bits of the symbol have changed value (e.g., changed value while being stored to the one or more memory arrays 215 and/or while being read from the one or more memory arrays 215). A corrupted symbol in data and an error in data may be used interchangeably. For example, the encoder 240 may generate the second parity information using one or more single symbol correction (SSC) schemes, as described in greater detail in connection to FIG. 3. Alternatively, the encoder 240 may generate the second parity information using a DSC scheme, as described in greater detail in connection with FIG. 4. The second parity information may include a given quantity data, such as 32 bits (e.g., four symbols). Accordingly, the codeword 230 may include 72 symbols (e.g., 72 bytes). Symbols of the codeword 230 may be ordered. For example, each symbol of the codeword 230 may have a respective position, such as a symbol index. Said another way, the codeword 230 may be represented as a vector y of symbols y.sub.i, where i{0, 1, 2 . . . 71}. In such a representation, the symbol y; is the i.sup.th symbol of the codeword 230 (e.g., the symbol y.sub.i is in the i.sup.th position of the codeword 230).

(35) In some examples, the memory system may obtain, from the host system, a command to read the data packet 220 from the one or more memory arrays 215 (e.g., a read command). To read the data packet 220, the memory system may retrieve the codeword 230 from the one or more memory arrays 215. The memory system may decode the codeword 230 to correct and/or detect one or more errors in the codeword 225 using a decoder 245. As described in greater detail in connection to FIG. 5, to decode the codeword 230, the memory system may calculate a syndrome (e.g., one or more values that indicate information associated with the one or more errors in the codeword 225). Using the syndrome, the memory system may attempt to detect one or more errors in the codeword 225. If the memory system detects no errors in the codeword 225, the memory system may issue the codeword 225 to the next stage of the read data path 210 (e.g., to a decoder 250). Alternatively, if the memory system detects one or more correctable errors in the codeword 225, then the memory system may correct the one or more correctable errors using one or more combinational circuits. Subsequently, the memory system may issue the codeword 225 to the next stage of the read data path 210. The memory system may decode the codeword 225 to correct and/or detect one or more errors in the data packet 220 using the decoder 250. For example, the memory system may perform a CRC operation to detect and/or correct the one or more errors in the data packet. The memory system may thus provide the corrected data packet 220 to the host system. In some examples, such as if the memory system detected one or more uncorrectable errors, the memory system may provide a message to the host indicating that the data packet includes the one or more uncorrectable errors.

(36) By encoding a codeword 225 using the encoder 240, the system 200 may enable generating parity information for the DSC error scheme using one or more combinational circuits. Such an implementation may improve the performance of encoding the codeword 225, such as by reducing the quantity of resources (e.g., processing resources and/or energy resources) used to encode the codeword 225, by increasing the speed at which the encoder 240 encodes the codeword 225, and reducing the complexity of processing circuitry used to encode the codeword 225.

(37) Further, by decoding a codeword 230 using the decoder 245, the system 200 may enable the DSC error scheme using one or more combinational circuits. Such an implementation may improve the performance of decoding the codeword 230, such as by reducing the quantity of resources (e.g., processing resources and/or energy resources) used to decode the codeword 230, by increasing the speed at which the decoder 245 decodes the codeword 230, and reducing the complexity of processing circuitry used to decode the codeword 230.

(38) As indicated above, FIG. 2 is provided as an example. Other examples may differ from what is described with regard to FIG. 2.

(39) FIG. 3 is a diagram illustrating an example of a data structure 300 capable of error control in memory systems using combinational circuits. A memory apparatus, such as the memory system 110, may manage the data structure 300. The data structure 300 may include a codeword 305, which may be an example of a codeword 230. For example, the codeword 305 may include a payload 310, which may include a data packet 220 and/or a codeword 225.

(40) The codeword 305 may include parity information 315 configured to correct multiple corrupted symbols in the payload 310. For example, the codeword 305 may be generated by an encoder, such as the encoder 240. The parity information 315 may be generated using one or more error correction schemes that are each configured to correct a respective error in the payload 310, such as one or more SSC schemes. To enable correcting multiple errors, the memory system may partition the payload 310 into multiple portions 320, such as the portion 320-a and the portion 320-b. The memory system may generate portions 325 of the parity information 315, such as a portion 325-a and a portion 325-b, using the corresponding portions 320-a and 320-b of the payload 310. For example, the memory system may generate the portion 325-a of the parity information 315 by applying a first error correction scheme to the portion 320-a of the payload 310 and may generate the portion 325-b of the parity information 315 by applying a second error correction scheme to the portion 320-b of the payload 310. Each portion 325 of the parity information 315 may be configured to correct a single error in the corresponding portion 320 of the payload 310. For example, the portion 325-a of the parity information 315 and the portion 325-b of the parity information may each be a respective SSC code. Accordingly, by arranging the payload 310 into multiple (e.g., two) portions 320, the data structure 300 may enable correcting up to two errors in the payload 310.

(41) In some examples, the memory system may configure the portions 320 to mitigate the likelihood of multiple errors occurring in a single portion 320. For example, the memory system may configure the portions 320 such that symbols stored to consecutive portions of the memory system, such as symbols stored to neighboring portions of a word line and/or symbols stored to neighboring word lines, are arranged in different portions 320 of the payload 310. Accordingly, in the event of an error which corrupts a word line and/or neighboring word lines, the memory system may mitigate the likelihood of multiple symbols in the same portion 320 being corrupted.

(42) As indicated above, FIG. 3 is provided as an example. Other examples may differ from what is described with regard to FIG. 3.

(43) FIG. 4 is a diagram illustrating an example of an encoder 400 capable of error control in memory systems using combinational circuits. The encoder 400 may be implemented in a data path of a memory system, such as the write data path 205 of the memory system 110. The encoder 400 may be configured to encode a payload 405, such as a data packet 220 and/or a codeword 225, into a codeword 410 having parity information 415 capable of correcting up to two errors. For example, the encoder 400 may be an example of the encoder 240.

(44) The encoder 400 may encode the payload 405 using one or more combinational circuits in accordance with a DSC error correction scheme, such as a Reed-Solomon scheme (e.g., the parity information 415 may be a Reed-Solomon code). In accordance with the DSC error correction scheme, symbols of the payload 405 and/or the parity information 415 may be represented as elements of an algebraic field, such as a finite field (e.g., a Galois field). As described herein, an algebraic field is a set of elements on which operations including addition, subtraction, multiplication, and division are defined and satisfy one or more field rules. A finite field, which may also be called a Galois field, is a field having a finite quantity of elements. Finite fields may be defined, in part, by the quantity of elements included in the field. For example, a finite field having two elements may be referred to as the GF(2) field, a finite field having four elements may be referred to as the GF(4) field and/or the GF(22) field, and so on. Thus, because symbols of the payload 405 and/or the parity information 415 may include eight bits, each possible symbol may be represented as a respective element of the GF(28) field.

(45) The encoder 400 may operate on such symbols according to the arithmetic (e.g., the one or more field rules) of the GF(28) field. For example, the encoder 400 may perform operations between element of the GF(28) field, such as addition, subtraction, multiplication, and/or division, such that the result of an operation is an element of the GF(28) field (e.g., using modulo (mod) arithmetic). Each non-zero element of a finite field may be written in terms of a primitive element . For example, each non-zero element of a finite field may be written as a, where i is a natural number. Additionally, or alternatively, elements of a finite field may be represented as polynomials, and each element of the field may be written as a generator polynomial raised to a power. For example, the GF(28) field may have a generator polynomial p(x)=x.sup.8+x.sup.4+x.sup.3+x.sup.2=1.

(46) To generate the parity information 415, the encoder 400 may use a DSC code having a generator polynomial g(x)=x.sup.4+.sup.76.sup.3+2512+.sup.81x+.sup.10. The encoder 400 may, using the one or more combinational circuits, multiply the payload 405 by a parity matrix 420. The parity matrix 420 may be defined as PT, as shown in equation 1 below, where r.sub.i(x)=x.sup.NK+i mod g (x), N is the quantity of symbols in the codeword 410 (e.g., 72 symbols), and K is the quantity of symbols in the codeword 505 (e.g., 68 symbols). In equation 1, each element r; (x) is an element of the algebraic field represented as a polynomial (e.g., a polynomial function taking x as an independent variable).

(47) $\begin{array}{cc}{P}^T=\left[\begin{array}{c}-r_{0}x\\ -r_1\left(x\right)\\ .Math.\\ -r_{K-1}\left(x\right)\end{array}\right]& \left(1\right)\end{array}$

(48) For example, if the payload 405 and the parity information 415 are denoted as vectors d and p of symbols, respectively, then the parity information 415 may be obtain as shown in equation 2.
p=dP.sup.T(2)

(49) To enable multiplication of the payload 405 by the parity matrix 420, the parity matrix 420 may be encoded as a matrix of symbols (e.g., may be encoded in a binary representation). After generating the parity information 415, the encoder 400 may combine the payload 405 and the parity information 415 (e.g., by appending the parity information 415 to the payload 405) to generate the codeword 410.

(50) By encoding a payload 405 using the parity matrix 420, the encoder 400 may enable generating parity information for the DSC error scheme using one or more combinational circuits. Such an implementation may improve the performance of encoding the payload 405, such as by reducing the quantity of resources (e.g., processing resources and/or energy resources) used to encode the payload 405, by increasing the speed at which the encoder 400 encodes the payload 405, and reducing the complexity of processing circuitry used to encode the payload 405.

(51) As indicated above, FIG. 4 is provided as an example. Other examples may differ from what is described with regard to FIG. 4.

(52) FIG. 5 is a diagram illustrating an example of a system 500 that supports error control in memory systems using combinational circuits. The system 500 may include aspects of and/or may be implemented by a memory apparatus, such as the memory system 110 and/or a memory device 120. For example, the system 500 may be implemented in a data path of the memory system, such as the read data path 210 of the memory system 110. The system 500 may include one or more components configured to decode a codeword 505. The codeword 505 may be an example of the codeword 230 as described with reference to FIG. 2.

(53) The system 500 may be configured to determine and/or correct multiple errors in the codeword 505. For example, the codeword 505 may be represented as a set (e.g., a vector), denoted as y, of symbols where a symbol at the i.sup.th position in the codeword 505 may be denoted as y.sub.i. The system 500 may generate an error vector 590, denoted as e, that is a vector of symbols (e.g., symbols representing an error in the codeword 505), where the i.sup.th position in the error vector may be denoted as e.sub.i. If the system 500 determines that a symbol y.sub.i includes an error, then the element e.sub.i may be equal to an error value associated with the error. Alternatively, if the system 500 does not detect an error in the symbol y.sub.i, then the element e.sub.i may be equal to zero (e.g., the zero element of the algebraic field). The system 500 may generate a corrected codeword, denoted as d, by combining the codeword 505 and the error vector 590. For example, the corrected codeword may be calculated by d=y+e. As described herein, an error value e.sub.i is a symbol that, when added to the symbol y.sub.i, produces a corrected symbol d.sub.i, as described in greater detail elsewhere herein.

(54) The system 500 may include a syndrome generator 510 configured to calculate a syndrome 515 for the codeword 505. The syndrome 515 may include one or more syndrome values S.sub.1, S.sub.2, S.sub.3, and S.sub.4 that may be elements of the algebraic field, as described in greater detail in connection to FIG. 6. The syndrome generator 510 may provide the syndrome 515 to a decoding value generator 530.

(55) The decoding value generator 520 may be configured to, using one or more combinational circuits taking the syndrome 515 as a set of inputs, generate one or more decoding values 525 denoted as A, B, C, D, and E, as described in greater detail in connection to FIG. 7. Because the one or more decoding values 525 may be calculated using operations between the one or more syndrome values (e.g., additions and/or multiplications of the one or more syndrome values), each decoding value 525 may be an element of the algebraic field (e.g., each decoding value 525 may be an 8-bit symbol).

(56) The one or more decoding values 525 may indicate information associated with the error vector e. The system 500 may use a first subset of the decoding values 525 to determine one or more positions i of non-zero error values e; in the error vector e, and may use a second subset of the decoding values 525 to determine the error values e.sub.i.

(57) The decoding value generator 520 may provide one or more of the decoding values 525 to one or more coefficient generators 530. A coefficient generator 530 may be configured to obtain a decoding value 525 and output one or more coefficients of an error position equation using the decoding value 525. Each coefficient may correspond to a respective position (a respective symbol index) in the codeword 505. For example, as explained in greater detail in connecting to FIG. 8, for i{0, 1, 2, . . . 71}, the coefficient generator 530-a may obtain the decoding value A and may output one or more coefficients A.sup.2i. The coefficient generator 530-b may obtain the decoding value B and may output one or more coefficients B.sup.i. The coefficient generator 530-c may obtain the decoding value E and may output one or more coefficients E.sup.i.

(58) The decoding value generator 520 and/or the coefficient generators 530 may provide the coefficients A.sup.2i and B, as well as the decoding value C, to an error position generator 535. The error position generator 535 may include one or more combinational circuits 540 configured to determine whether one or more symbols of the codeword 505 include an error. In some implementations, the error position generator 535 may include a quantity of combinational circuits 540 equal to the quantity of symbols of the codeword 505.

(59) In such examples, a combinational circuit 540 (e.g., the i.sup.th combinational circuit 540) may be configured to determine whether the symbol y; of the codeword 505 includes an error. For example, the combinational circuit 540 may obtain, as inputs, the coefficients A.sup.2i and B.sup.i, as well as the decoding value C. The combinational circuit 540 may determine whether the inputs satisfy an equation. For example, as described in greater detail in connection to FIG. 7, the combinational circuit 540 may determine whether the equation A.sup.2i+B.sup.i+C=0 is satisfied (e.g., if the sum of the coefficients A.sup.2i, B.sup.i, and the decoding value decoding value C is equal to zero). If the inputs satisfy the equation, then the combinational circuit 540 may detect that an error exists in the i.sup.th position of the codeword 505. Alternatively, if the inputs do not satisfy the equation, then the combinational circuit 540 may not detect that an error exists in the i.sup.th position of the codeword 505.

(60) To determine whether the inputs satisfy the equation, the combinational circuit 540 may include an adding circuit configured to compute the sum of the inputs and provide the result to a logic gate 545, such as a not-or (NOR) gate. If the result is equal to zero, then the logic gate 545 may output a first value (e.g., a logic 1). Otherwise, the logic gate 545 may output a second value (e.g., a logic 0). Accordingly, the error position generator 535 may output one or more error position values (e.g., a respective error position value for each combinational circuit 540), where the i.sup.th error position value indicates whether the i.sup.th symbol of the codeword 505 contains an error.

(61) The error position generator 535 may provide an indication of the quantity of errors in the codeword 505 to a flag generator 550. For example, the error position generator 535 may provide the one or more error position values to a weight circuit 555. The weight circuit 555 may determine the quantity of errors in the codeword 505 (e.g., by summing the one or more error position values), and may provide the quantity to the flag generator 550.

(62) The flag generator 550 may be configured to extract information associated with one or more errors in the codeword 505 using the syndrome 515 (e.g., provided by the syndrome generator 510), the one or more decoding values 525 (e.g., provided by the decoding value generator 520), and/or the quantity of errors in the codeword 505 (e.g., provided by the weight circuit 555). For example, the flag generator 550 may generate one or more flags 560 indicating information associated with the one or more errors. For example, if the flag generator 550 determines that there are no errors in the codeword 505, then the flag generator 550 may set the value of a flag 560-a (e.g., set the value to a logic 1) and may reset the values of flags 560-b through 560-e (e.g., may set the respective values of the flags 560-b through 560-e to a logic 0). Alternatively, if the flag generator 550 determines that the codeword 505 includes a correctable error, then the flag generator 550 may set the value of a flag 560-d. Additionally, the flag generator 550 may indicate whether the codeword 505 includes one error or two errors by setting the flags 560-b or 560-c, respectively. If the flag generator 550 determines that the codeword 505 includes an uncorrectable error, then the flag generator 550 may set the value of the flag 560-c. The flag generator 550 may provide the flags 560 to a host system 105 and/or a controller, such as the local controller 125 and/or the memory system controller 115.

(63) The decoding value generator 520 and/or the coefficient generators 530 may provide the coefficients E.sup.i, along with the decoding values B and D, to an error value generator 565. In some examples, the error position generator 535 may provide the one or more error position values to the error value generator 565. The error value generator 565 may be configured to determine one or more error values, where an error value et satisfies the equation Be.sub.i=D+E.sup.i, as described in greater detail in connection to FIG. 7. For example, because the algebraic field is finite, the error value generator 565 may test all possible values of e; for each position i indicated by the error position values to determine the one or more error values that satisfy the equation.

(64) Additionally, or alternatively, the error value generator 565 may include a combinational circuit 570, one or more combinational circuits 575, and one or more combinational circuits 580 configured to determine the one or more error values. The combinational circuit 570, along with a given set of the combinational circuits 575 and 580 (e.g., the i.sup.th combinational circuits 575 and 580) may be configured to determine the error value e; using the equation Be.sub.i=D+E.sup.i. For example, the i.sup.th combinational circuit 575 may compute the sum of D and E.sup.i. Additionally, the combinational circuit 570 may obtain the decoding value B and may determine the inverse of the decoding value B (e.g., B.sup.1, the inverse element of B in the algebraic field). The combinational circuit 580 may compute the product B.sup.1 (D+E.sup.i) to compute the error value et.

(65) To determine B.sup.1, the combinational circuit 570 may calculate B.sup.1 using a set of combinational circuits, such as one or more squarer circuits and/or one or more multiplicative circuits, as described in greater detail in connection to FIG. 7. For example, an inverse element .sup.1 of an element a in a Galois field GF(2.sup.m) can be calculated using .sup.1=a.sup.2 a.sup.2.sup.2 a.sup.2.sup.3 . . . a.sup.2.sup.m-1. Accordingly, if B is an element of a Galois field GF(2.sup.8), then B.sup.1=B.sup.2B.sup.4 B.sup.8B.sup.16 B.sup.32B.sup.64 B.sup.128, and B.sup.1 may be calculated using the one or more squarer circuits and/or the one or more multiplicative circuits.

(66) Additionally, or alternatively, to determine B.sup.1, the combinational circuit 570 may use a mapping between one or more elements of the algebraic field and one or more inverse elements of the algebraic field. The mapping may include a table (e.g., a look-up table) which, for each element in the algebraic field, includes an association between the element and the inverse of the element. Thus, the combinational circuit 570 may look up the value B in the mapping to determine B.sup.1.

(67) The combinational circuit 580 may provide the error value e; to one or more logic gates 585 (e.g., one or more AND gates). The one or more logic gates 585 may be configured to combine the error values e.sub.i generated by the error value generator 565 to generate the error vector 590, denoted by e. For example, the one or more logic gates 585 may obtain the one or more error position values from the error position generator 535. To generate the i.sup.th symbol of the error vector 590, the one or more logic gates 585 may determine whether the i.sup.th error position value indicates that the i.sup.th symbol of the codeword 505 includes an error. If the one or more logic gates 585 determine that the i.sup.th symbol of the codeword 505 includes an error, then the one or more logic gates 585 may output the error value e.sub.i for the i.sup.th symbol of the error vector 590. Alternatively, if the one or more logic gates 585 determine that the i.sup.th symbol of the codeword 505 does not include an error, then the one or more logic gates 585 may output zero (e.g., the zero element of the algebraic field) for the i.sup.th symbol of the error vector 590.

(68) Accordingly, the system 500 may output the error vector 590. To correct the codeword 505, the memory system (e.g., using the system 500 or another component) may add the error vector 590 to the codeword 505. Said another way, the corrected codeword d may be calculated according to d=y+e.

(69) In some examples, the system 500 may be organized into one or more stages. For example, the system 500 may include a first stage corresponding to the syndrome generator 510, a second stage corresponding to the decoding value generator 520, a third stage corresponding to the coefficient generators 530, a fourth stage corresponding to the error position generator 535, and/or a fifth stage corresponding to the error value generator 565, among other examples. In such examples, each stage may be associated with a respective buffer, such as a volatile memory array 135 that includes a register. The system may temporarily store the output of stage to the respective buffer (e.g., may cache the output to a buffer) to control timing of the system 500. For example, during a first duration, the system 500 may generate the syndrome 515 and may store the syndrome 515 to a first buffer of the first stage. During a second duration subsequent to the first duration, the system 500 may issue the syndrome 515 from the first buffer to the decoding value generator 520. The decoding value generator 520 may generate the decoding values 525 and may store the decoding values 525 to a second buffer of the second stage. During a third duration subsequent to the second duration, the system 500 may issue the decoding values 525 from the second buffer to the coefficient generators 530. The coefficient generators 530 may generate the coefficients and may store the coefficients to a third buffer of the third stage. During a fourth duration subsequent to the third duration, the system 500 may issue the decoding values 525 from the second buffer and/or may issue the coefficients from the third buffer to the error position generator 535. The error position generator 535 may generate the one or more error position values and may store the one or more error position values to a fourth buffer of the fourth stage. During a fifth duration subsequent to the fourth duration, the system 500 may issue the decoding values 525 from the second buffer, may issue the coefficients from the third buffer, and/or may issue the one or more error position values from the fourth buffer to the error value generator 565 The error value generator 565 may generate the one or more error values and may store the one or more error values to a fifth buffer of the fifth stage. By implementing one or more buffers between stages of the system 500, the system 500 may control the timing of generating the corrected codeword, which may allow the system 500 to reduce the rate of power consumption (e.g., by increasing the duration between consecutive stages), which may allow for improved peak-power management.

(70) By decoding a codeword 505, the system 500 may enable the DSC error scheme using one or more combinational circuits. Such an implementation may improve the performance of decoding the codeword 505, such as by reducing the quantity of resources (e.g., processing resources and/or energy resources) used to decode the codeword 505, by increasing the speed at which the system 500 decodes the codeword 505, and reducing the complexity of processing circuitry used to decode the codeword 505.

(71) As indicated above, FIG. 5 is provided as an example. Other examples may differ from what is described with regard to FIG. 5.

(72) FIG. 6 is a diagram illustrating an example of a system 600 that supports error control in memory systems using combinational circuits. The system 600 may be an example of a syndrome generator, such as the syndrome generator 510. For example, the system 600 may be implemented within a decoder for a memory system, such as within a decoder 245 of a read data path 210 of the memory system 110.

(73) The system 600 may be configured to obtain a codeword 605, which may be a codeword 505 and may be denoted as y, and generate one or more syndrome values 610 of a syndrome. For example, the system 600 may be configured to generate a syndrome value 610-a, denoted by S.sub.1, using a combinational circuit 615-a, may be configured to generate a syndrome value 610-b, denoted by S.sub.2, using a combinational circuit 615-b, may be configured to generate a syndrome value 610-c, denoted by S.sub.3, using a combinational circuit 615-c, and/or may be configured to generate a syndrome value 610-d, denoted by S.sub.4, using a combinational circuit 615-d.

(74) The system 600 may generate a syndrome value 610 by multiplying (e.g., in accordance with the algebraic field) the codeword 605 by a power of a primitive element of the algebraic field using a combinational circuit 615. For example, the combinational circuit 615-a may multiply the codeword 605 by a to obtain S.sub.1, the combinational circuit 615-b may multiply the codeword 605 by .sup.2 to obtain S.sub.2, the combinational circuit 615-c may multiply the codeword 605 by .sup.3 to obtain S.sub.3, and the combinational circuit 615-d may multiply the codeword 605 by .sup.4 to obtain S.sub.4, as shown in equations 3 through 6.

(75) $\begin{array}{cc}{S}_1=y\left(\right)=\underset{i=0}{\overset{71}{.Math.}}{y}_i{}^i=y{A}_1& \left(3\right)\end{array}$$\begin{array}{cc}{S}_2=y\left({}^2\right)=\underset{i=0}{\overset{71}{.Math.}}{y}_i{}^{2i}=y{A}_2& \left(4\right)\end{array}$$\begin{array}{cc}{S}_3=y\left({}^3\right)=\underset{i=0}{\overset{71}{.Math.}}{y}_i{}^{3i}=y{A}_3& \left(5\right)\end{array}$$\begin{array}{cc}{S}_4=y\left({}^4\right)=\underset{i=0}{\overset{71}{.Math.}}{y}_i{}^{4i}=y{A}_4& \left(6\right)\end{array}$

(76) As shown in equations 3 through 6, each syndrome value 610 may be calculated by multiplying the codeword 605 by a respective vector A.sub.1, A.sub.2, A.sub.3, or A.sub.4 defined in table 1.

(77) TABLE-US-00001 TABLE 1 $A_1=\left[\begin{array}{c}1\\ \\ {}^2\\ {}^3\\ {}^4\\ .Math.\\ {}^{71}\end{array}\right]$ $A_2=\left[\begin{array}{c}1\\ {}^2\\ {}^4\\ {}^6\\ {}^8\\ .Math.\\ {}^{142}\end{array}\right]$ $A_3=\left[\begin{array}{c}1\\ {}^3\\ {}^6\\ {}^9\\ {}^{12}\\ .Math.\\ {}^{213}\end{array}\right]$ $A_4=\left[\begin{array}{c}1\\ {}^4\\ {}^8\\ {}^{12}\\ {}^{16}\\ .Math.\\ {}^{284}\end{array}\right]$

(78) As indicated above, FIG. 6 is provided as an example. Other examples may differ from what is described with regard to FIG. 6.

(79) FIG. 7 is a diagram illustrating an example of a system 700 that supports error control in memory systems using combinational circuits. The system 700 may be an example of a decoding value generator, such as the decoding value generator 520. For example, the system 700 may be implemented within a decoder for a memory system, such as within a decoder 245 of a read data path 210 of the memory system 110. The system 700 may be configured to obtain one or more syndrome values 705 (shown as 705-a, 705-b, 705-c, and 705-d), which may be the syndrome values 610-a, 610-b, 610-c, and 610-d and may be denoted as S.sub.1, S.sub.2, S.sub.3, and S.sub.4, respectively, and generate one or more decoding values 710, which may be the one or more decoding values 525.

(80) To generate the decoding values 710, the system 700 may include one or more combinational circuits. For example, the system 700 may include one or more addition circuits 715 configured to obtain two inputs and output the sum of the inputs in accordance with the algebraic field. Additionally, the system 700 may include one or more multiplicator circuits 720 configured to obtain two inputs and output the product of the inputs in accordance with the algebraic field. Additionally, the system 700 may include one or more squarer circuits 725 configured to obtain an input and output the square of the input in accordance with the algebraic field. Additionally, the system 700 may include one or more cubator circuits 730 configured to obtain an input and output the cube of the input in accordance with the algebraic field.

(81) Using the addition circuits 715, the multiplicator circuits 720, the squarer circuits 725, and the cubator circuits 730, the system 700 may generate a decoding value 710-a, denoted as A, a decoding value 710-b, denoted as B, a decoding value 710-c, denoted as C, a decoding value 710-d, denoted as D, and a decoding value 710-e, denoted as E, as shown in equations 7 through 11.

(82) $\begin{array}{cc}A=S_1{S}_3+S_2^2& \left(7\right)\end{array}$
B=S.sub.2S.sub.3+S.sub.1S.sub.4(8)

(83) $\begin{array}{cc}C=S_3^2+S_2{S}_4& \left(9\right)\end{array}$$\begin{array}{cc}D=S_1^2{S}_3+S_1{S}_2^2& \left(10\right)\end{array}$$\begin{array}{cc}E=S_2^3+S_1^2{S}_4& \left(11\right)\end{array}$

(84) The one or more combinational circuits may perform respective operations in accordance with the algebraic field. For example, an addition circuit 715 may compute the XOR of the inputs and output the result. The system 700 may perform multiplicative operations as a sum of symbols in terms of the primitive element . For example, equation 12 may illustrate a notation that enables multiplying, using the addition circuit 715, a symbol a having a j.sup.th component (e.g., a j.sup.th bit) denoted by .sub.j by a symbol b having a j.sup.th component denoted by b.sub.j.

(85) $\begin{array}{cc}ab=\left(\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^j\right)b=\underset{j=0}{\overset{7}{.Math.}}{a}_j\left(b{}^j\right)& \left(12\right)\end{array}$

(86) Equation number 13 may illustrate a notation that enables squaring, using the multiplicator circuit 720, a symbol a.

(87) 0$\begin{array}{cc}{a}^2={\left(\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^j\right)}^2=\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^{2j}=a\left[\begin{array}{c}1\\ {}^2\\ {}^4\\ {}^6\\ {}^8\\ {}^{10}\\ {}^{12}\\ {}^{14}\end{array}\right]& \left(13\right)\end{array}$

(88) Equation number 14 may illustrate a notation that enables cubing, using the squarer circuit 725, a symbol a.

(89) $\begin{array}{cc}{a}^3={\left(\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^j\right)}^3={\left(\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^j\right)}^2\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^j=\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^{2j}\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^j=\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^j+\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^j=\underset{j=0}{\overset{7}{.Math.}}{a}_j{}^{3j}+\underset{j=0}{\overset{6}{.Math.}}\underset{k=j+1}{\overset{7}{.Math.}}{a}_j{a}_k\left({}^{2j+k}+a^{j+2k}\right)& \left(14\right)\end{array}$

(90) The system 700 may provide a first subset of the decoding values 710 to a coefficient generator (e.g., the coefficient generator 530) and/or an error position generator (e.g., the error position generator 535). The first subset may include the decoding value 710-a, the decoding value 710-b, and the decoding value 710-c. The coefficient generator may provide a first one or more coefficients associated with the decoding value 710-a and the decoding value 710-b to the error position generator. The error position generator may identify whether the i.sup.th symbol of a codeword (e.g., the codeword 505) includes an error. Additionally, the system 700 may provide a second subset of the decoding values to the coefficient generator and/or an error value generator (e.g., the error value generator 565). The second subset may include the decoding value 710-b, the decoding value 710-d, and the decoding value 710-e. The coefficient generator may provide a second one or more coefficients to the error value generator. The error value generator may generate the error value for the i.sup.th symbol of a codeword et.

(91) For example, the errors of the codeword may be described in terms of an error locator polynomial (x) that may indicate a position of the errors and an error equation polynomial (x) that may indicate the value of the errors. The key equations of the error locator polynomial may be written in terms of unknown coefficients .sub.1 and .sub.2 of the error locator polynomial, as shown by equations 15 and 16.
S.sub.3.sub.1+S.sub.2.sub.2=S.sub.4(15)
S.sub.2.sub.1+S.sub.1.sub.2=S.sub.3(16)

(92) If A0, then the rank of the key equations 15 and 16 is full, and the codeword includes two errors. In this case, .sub.1 and .sub.2 may be written in terms of the syndrome values 705 and A, as shown in equations 17 and 18.

(93) $\begin{array}{cc}{}_1=\frac{S_2{S}_3+S_1{S}_4}{A}& \left(17\right)\end{array}$$\begin{array}{cc}{}_2=\frac{S_3^2+S_2{S}_4}{A}& \left(18\right)\end{array}$

(94) Further, the error equation polynomial (x) may be written in terms of the syndrome values 705 and A, as shown in equation 19.

(95) $\begin{array}{cc}\left(x\right)=S_1+\frac{S_2^3+S_1^2{S}_4}{A}x=S_1+\left(S_2+S_1{}_1\right)x& \left(19\right)\end{array}$

(96) Assuming that x=.sup.i, the error value e; is thus given by equation 20.

(97) $\begin{array}{cc}{e}_i=\frac{\left(x\right)}{{}^{}\left(x\right)}=\frac{S_1}{{}_1}+\frac{S_2}{{}_1}x+S_{1}x& \left(20\right)\end{array}$

(98) The error locator polynomial may thus be written in terms of A, B, and C, as shown by equation 21.
A(x)=A+Bx+Cx.sup.2(21)

(99) Similarly, the equation for the error value e; may be written in terms of B, D, and E, as shown in equation 22.
Be.sub.i=S.sub.1A+(S.sub.2A+S.sub.1B)x=D+Ex(22)

(100) Accordingly, if (x)=0, then equations 23 and 24 are satisfied when there is an error in the i.sup.th symbol of the codeword.
A.sup.2i+B.sup.i+C=0(23)
e.sub.iB+D+Ea.sup.1=0(24)

(101) Alternatively, if A=0, then the rank of the key equations 16 and 17 is not full, and the codeword includes a single error. In this case, .sub.2=0, and .sub.1 may be written in terms of the syndrome values 705, as shown in equation 25.

(102) $\begin{array}{cc}{}_1=\frac{S_2}{S_1}& \left(25\right)\end{array}$

(103) Thus, the error locator polynomial may be written as shown in equation 26.
S.sub.1(x)=S.sub.1+S.sub.2x(26)

(104) Accordingly, the error equation polynomial may be written as shown in equation 27.
(x)=S.sub.1 (27)

(105) Further, the equation for the error value e.sub.i may be written as shown in equation 28.

(106) $\begin{array}{cc}{e}_i=\frac{S_1^2}{S_2}& \left(28\right)\end{array}$

(107) Table 2 may summarize equations 7 through 28 in the case in which the codeword includes two errors (e.g. A0) and in the case in which the codeword includes one error (e.g., A=0).

(108) TABLE-US-00002 TABLE 2 Two errors One error $A=S_1{S}_3+S_2^{2}0$ A = 0 B = S.sub.25.sub.3 + S.sub.1S.sub.4 B = S.sub.2 $C=S_3^2+S_2{S}_4$ C = S.sub.3 $D=S_1^2{S}_3+S_1{S}_2^2$ 0$D=S_1^2$ $E=S_2^3+S_1^2{S}_4$ E = 0 (x)= 1 + .sub.1x + .sub.2x.sup.2 '(x) = .sub.1 (x) = S.sub.1 + (S.sub.2 + S.sub.1.sub.1) $\begin{array}{cc}{}_1=\frac{B}{A}& {}_2=\frac{C}{A}\end{array}$ $\begin{array}{cc}{}_1=\frac{S_2}{S_1}=\frac{S_3}{S_1}& {}_2=0\end{array}$ $\left(x\right)=S_1+\left(S_2+\frac{S_{1}B}{A}\right)x$ (x) = S.sub.1 $e_i=\frac{\left(x\right)}{{}^{}\left(x\right)}=\frac{S_1+\left(S_2+S_1{}_1\right)x}{{}_1}$ $e_i=\frac{S_1}{{}_1}=\frac{S_1^2}{S_2}$ = 0 .Math. A.sup.2i + B.sup.i + C = 0 = 0 .Math. S.sub.2.sup.i + S.sub.3 = 0 i 0, . . . , 71 i 0, . . . , 71 Be.sub.i = D + E.sup.i $S_2{e}_i=S_1^2$

(109) As indicated above, FIG. 7 is provided as an example. Other examples may differ from what is described with regard to FIG. 7.

(110) FIG. 8 is a diagram illustrating an example of a system 800 that supports error control in memory systems using combinational circuits. The system 800 may include a coefficient generator 805, which may be a coefficient generator 530. For example, the system 800 may be implemented within a decoder for a memory system, such as within a decoder 245 of a read data path 210 of the memory system 110. The system 800 may be configured to obtain a decoding value and output one or more coefficients 810, such as a coefficient 810-a, a coefficient 810-b, through a coefficient 810-N based on linear combinations 815 of the decoding value.

(111) As described herein, a linear combination 815 of a decoding value may be a single bit equal to the sum (e.g., the XOR) of each bit of the decoding value, where each bit is multiplied by the respective value (e.g., multiplied by one or zero). For example, the kth linear combination 815 (LC.sup.k) of the decoder value A, in which A.sub.j may be the j.sup.th bit of the decoder value A, may be defined by a vector a.sup.k having values a.sup.k equal to one or zero, as shown in equation 29. Each vector a.sup.k may include a unique sequence of ones and zeros. By way of example, a.sup.0=[0, 0, 0, 0, 0, 0, 0, 0], a.sup.1=[0, 0, 0, 0, 0, 0, 0, 1], a.sup.2=[0, 0, 0, 0, 0, 0, 1, 0], and so on.

(112) $\begin{array}{cc}L{C}^k=\underset{j=0}{\overset{7}{.Math.}}{a}_j^k{A}_j& \left(29\right)\end{array}$

(113) Each vector a.sup.k may include a unique sequence of ones and zeros. By way of example, suppose that A=[1, 1, 0, 1, 0, 1, 1, 1]. Further, suppose a.sup.0=[0, 0, 0, 0, 0, 0, 0, 0], a.sup.1=[0, 0, 0, 0, 0, 0, 0, 1], a.sup.2=[0, 0, 0, 0, 0, 0, 1, 0], and so on. In such an example, the linear combination LC.sup.1 of A would be given by equation 30.

(114) $\begin{array}{cc}L{C}^1=\underset{j=0}{\overset{7}{.Math.}}{a}_j^1{A}_j=0.Math.1+0.Math.1+0.Math.0+0.Math.1+0.Math.0+0.Math.1+0.Math.1+1.Math.1=0+0+0+0+0+0+0+1=1& \left(30\right)\end{array}$

(115) Accordingly, if the decoder value A and the vector a.sup.k are eight bit values, then there may be 256 possible linear combinations 815 of the decoder value (e.g., one linear combination for each possible vector a.sup.k, where k {0, 1, 2, . . . 255}).

(116) A given bit 820 of a coefficient 810 may be equal to a particular linear combination 815 of the decoder value associated with the coefficient 810. Said another way, the j.sup.th bit 820 of a coefficient may be equal to a particular linear combination LC.sup.k. For example, a first bit 820 of the coefficient A.sup.2i (e.g., (A.sup.2i)) may be equal to a linear combination LC.sup.4, a second bit 820 of the coefficient A.sup.2i (e.g., (A.sup.2i)) may be equal to a linear combination LC.sup.12, and so on. Although particular values for a.sup.k are given, such values are merely illustrative. Other choices for a.sup.k may be used to enable the techniques described herein.

(117) A coefficient generator 805 may be configured such that each bit 820 of each coefficient 810 is selected from the linear combinations 815. For example, a first coefficient generator 805 configured to generate the coefficients A.sup.2i (e.g., the coefficient generator 530-a) may select each bit (A.sup.2i).sub.j for each i{0, 1, 2 . . . 71} and each j{0, 1, 2 . . . 7}. The first coefficient generator 805 may provide the coefficients A.sup.2i to the error position generator 535 (e.g., may provide the i.sup.th coefficient A.sup.2i to the i.sup.th combinational circuit 540). Similarly, a second coefficient generator 805 configured to generate the coefficients Bai (e.g., the coefficient generator 530-b) may select each bit (B.sup.i).sub.j for each i{0, 1, 2 . . . 71} and each j {0, 1, 2 . . . 7}. The second coefficient generator 805 may provide the coefficients B.sup.i to the error position generator 535. Additionally, a third coefficient generator 805 configured to generate the coefficients E.sup.i (e.g., the coefficient generator 530-c) may select each bit (E.sup.i), for each i{0, 1, 2 . . . 71} and each j{0, 1, 2 . . . 7}. The third coefficient generator 805 may provide the coefficients E.sup.i to the error value generator 565 (e.g., may provide the i.sup.th coefficient E.sup.i to the i.sup.th combinational circuit 575).

(118) As indicated above, FIG. 8 is provided as an example. Other examples may differ from what is described with regard to FIG. 8.

(119) FIG. 9 is a flowchart of an example method 900 associated with error control in memory systems using combinational circuits. In some implementations, a memory system (e.g., the memory system 110) may perform or may be configured to perform the method 900. In some implementations, another device or a group of devices separate from or including the memory system (e.g., the host system 105, the host processor 150, and or the host interface 140) may perform or may be configured to perform the method 900. Additionally, or alternatively, one or more components of the memory system (e.g., a memory system controller 115, one or more memory devices 120, one or more local controllers 125, one or more memory arrays 130, one or more volatile memory arrays 135, a system 200, an encoder 400, a system 500, a system 600, a system 700, and/or a system 800) may perform or may be configured to perform the method 900. Thus, means for performing the method 900 may include the memory system and/or one or more components of the memory system. Additionally, or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory system, cause the memory system to perform the method 900.

(120) As shown in FIG. 9, the method 900 may include obtaining, from a host system, a command to read data (block 910). As further shown in FIG. 9, the method 900 may include retrieving a codeword associated with the data (block 920). As further shown in FIG. 9, the method 900 may include generating, based on the codeword, a syndrome (block 930). As further shown in FIG. 9, the method 900 may include generating one or more decoding values based on the syndrome and using one or more combinational circuits (block 940). As further shown in FIG. 9, the method 900 may include correcting one or more errors in the codeword using the one or more decoding values (block 950). As further shown in FIG. 9, the method 900 may include providing the data to the host system (block 960).

(121) The method 900 may include additional aspects, such as any single aspect or any combination of aspects described below and/or described in connection with one or more other methods or operations described elsewhere herein.

(122) In a first aspect, correcting the one or more errors comprises obtaining, at an error value generator, a subset of the one or more decoding values, generating an error value using the subset of the one or more decoding values, and adding the error value to the codeword to correct the one or more errors.

(123) In a second aspect, alone or in combination with the first aspect, generating the error value comprises calculating, using a second one or more combinational circuits, an inverse of a decoding value of the one or more decoding values.

(124) In a third aspect, alone or in combination with one or more of the first and second aspects, generating the error value comprises identifying, using a mapping between one or more elements of an algebraic field and one or more inverse elements of the algebraic field, an inverse of a decoding value of the one or more decoding values.

(125) In a fourth aspect, alone or in combination with one or more of the first through third aspects, the method 900 includes obtaining, at an error position generator coupled to a decoding value generator, a second subset of the one or more decoding values, generating, using a second one or more combinational circuits of the error position generator, one or more values indicating a position of the error value, and providing the one or more values to the error value generator, where generating the error value is based on the one or more values.

(126) In a fifth aspect, alone or in combination with one or more of the first through fourth aspects, the method 900 includes generating, using one or more coefficient generators, respective sets of coefficients of the second subset of decoding values, where generating the one or more values is based on the respective sets of coefficients.

(127) In a sixth aspect, alone or in combination with one or more of the first through fifth aspects, the method 900 includes generating, at a flag generator coupled to a decoding value generator, one or more values indicating whether the codeword includes the one or more errors.

(128) In a seventh aspect, alone or in combination with one or more of the first through sixth aspects, the method 900 includes obtaining, from the host system, a second command to store the data, generating, at an encoder and using a second one or more combinational circuits, first parity information, where the codeword includes the first parity information and the data, and storing the codeword to one or more memory arrays of the memory system.

(129) In an eighth aspect, alone or in combination with one or more of the first through seventh aspects, the method 900 includes generating, using a CRC operation, second parity information, where the codeword further includes the second parity information.

(130) In a ninth aspect, alone or in combination with one or more of the first through eighth aspects, the method 900 includes storing, at a buffer of the memory system, the syndrome, where generating the one or more decoding values comprises obtaining the syndrome from the buffer.

(131) In a tenth aspect, alone or in combination with one or more of the first through ninth aspects, the method 900 includes storing, at a buffer of the memory system, the one or more decoding values, where correcting the one or more errors comprises obtaining the one or more decoding values from the buffer.

(132) Although FIG. 9 shows example blocks of a method 900, in some implementations, the method 900 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 9. Additionally, or alternatively, two or more of the blocks of the method 900 may be performed in parallel. The method 900 is an example of one method that may be performed by one or more devices described herein. These one or more devices may perform or may be configured to perform one or more other methods based on operations described herein.

(133) In some implementations, a memory apparatus includes: a syndrome generator configured to generate a syndrome based on a codeword; a decoding value generator coupled to the syndrome generator, the decoding value generator configured to generate one or more decoding values based on the syndrome and using one or more combinational circuits; and an error value generator configured to generate an error value associated with the codeword based on the one or more decoding values.

(134) In some implementations, a method includes: obtaining, by a memory system and from a host system, a command to read data; retrieving, by the memory system, a codeword associated with the data; generating, by the memory system and based on the codeword, a syndrome; generating, by the memory system, one or more decoding values based on the syndrome and using one or more combinational circuits; correcting, by the memory system, one or more errors in the codeword using the one or more decoding values; and providing the data to the host system.

(135) In some implementations, a memory apparatus includes one or more controllers configured to: obtain, from a host system, a command to read data; retrieve a codeword associated with the data; generate, at a syndrome generator of the memory apparatus and based on the codeword, a syndrome; generate, at a decoding value generator of the memory apparatus, one or more decoding values based on the syndrome and using one or more combinational circuits; correct one or more errors in the codeword using the one or more decoding values; and provide the data to the host system.

(136) The foregoing disclosure provides illustration and description but is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the implementations described herein.

(137) Even though particular combinations of features are recited in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of implementations described herein. Many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. For example, the disclosure includes each dependent claim in a claim set in combination with every other individual claim in that claim set and every combination of multiple claims in that claim set. As used herein, a phrase referring to at least one of a list of items refers to any combination of those items, including single members. As an example, at least one of: a, b, or c is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination with multiples of the same element (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other ordering of a, b, and c).

(138) When a component or one or more components (or another element, such as a controller or one or more controllers) is described or claimed (within a single claim or across multiple claims) as performing multiple operations or being configured to perform multiple operations, this language is intended to broadly cover a variety of architectures and environments. For example, unless explicitly claimed otherwise (e.g., via the use of first component and second component or other language that differentiates components in the claims), this language is intended to cover a single component performing or being configured to perform all of the operations, a group of components collectively performing or being configured to perform all of the operations, a first component performing or being configured to perform a first operation and a second component performing or being configured to perform a second operation, or any combination of components performing or being configured to perform the operations. For example, when a claim has the form one or more components configured to: perform X; perform Y; and perform Z, that claim should be interpreted to mean one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (also possibly different) components configured to perform Z.

(139) No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles a and an are intended to include one or more items and may be used interchangeably with one or more. Further, as used herein, the article the is intended to include one or more items referenced in connection with the article the and may be used interchangeably with the one or more. Where only one item is intended, the phrase only one, single, or similar language is used. Also, as used herein, the terms has, have, having, or the like are intended to be open-ended terms that do not limit an element that they modify (e.g., an element having A may also have B). Further, the phrase based on is intended to mean based, at least in part, on unless explicitly stated otherwise. As used herein, the term multiple can be replaced with a plurality of and vice versa. Also, as used herein, the term or is intended to be inclusive when used in a series and may be used interchangeably with and/or, unless explicitly stated otherwise (e.g., if used in combination with either or only one of).