Basal Plane Dislocation Mitigation via Etching and Growth Interrupts

Abstract

A method of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer comprising the steps of providing a substrate, etching the substrate, converting BPDs to electrically benign threading edge dislocations, growing a first buffer layer on the substrate, creating a growth interrupt layer or second etch layer, growing a second buffer layer, growing a drift layer, and preventing BPDs from expanding into the drift layer. A device capable of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer comprising a substrate, a first buffer layer, a growth interrupt layer or etch layer, a second buffer layer and a drift layer. The drift layer carrier lifetime is not reduced. BPD expansion is prevented at current densities up to 12 kA/cm.sup.2.

Claims

1. A method of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer, comprising the steps of: providing a substrate; etching the substrate; converting BPDs to electrically benign threading edge dislocations; growing a first buffer layer on the substrate; creating a growth interrupt layer or second etch layer on the first buffer layer; growing a second buffer layer on the growth interrupt layer or second etch layer; growing a drift layer on the second buffer layer; and preventing BPDs from expanding into the drift layer.

2. The method of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer of claim 1, comprising the steps of: preventing BPD expansion at current densities up to 12 kA/cm.sup.2.

3. The method of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer of claim 2, further comprising the steps of: performing the step of etching the substrate in an inert gas, hydrogen gas, or precursors/hydrogen or a combination of gas mixture with the gas flowing between 1-200 slm at temperatures between 1400-1800 C; performing the step of etching the substrate in a pressure of 10-900 mbar; and performing the step of etching the substrate for 1 min-2 hr.

4. The method of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer of claim 3, wherein wherein the substrate is SiC; and wherein the SiC substrate is n-type, p-type, or semi-insulating (SI).

5. The method of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer of claim 4, further comprising the steps of: performing the step of etching the substrate at a temperature of 1665 C. in 80 slm H.sub.2 and 70 mbar; performing the step of etching the substrate for 50 min wherein the step of etching comprises the steps of increasing the pressure to 100 mbar; reducing the temperature to 1620 C.; growing the buffer layer to 6 m at 5 m/h; resulting in an electron concentration of 318.sup.18 cm.sup.3. reducing the pressure to 70 mbar; increasing the temperature to 1665 C.; maintaining the conditions for 50 min; increasing the pressure to 100 mbar; decreasing the temperature to 1620 C.; growing a 0.5 m second etch layer; and growing a 15 m drift layer at 10 m/h with an electron concentration of 510.sup.15 cm.sup.3.

6. The method of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer of claim 5, wherein basal plane dislocations (BPDs) did not expand until a power density of 13 kW/cm.sup.2 was applied; and wherein 50 cm.sup.2 expanded.

7. A capable of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer, comprising: a substrate; a first buffer layer on the substrate; a growth interrupt layer or etch layer on the first buffer layer on the substrate; a second buffer layer on the growth interrupt layer or etch layer; and a drift layer on the second buffer layer.

8. A device capable of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a doped buffer layer into an epitaxial device/active layer of claim 7, wherein basal plane dislocations (BPDs) did not expand until a power density of 13 kW/cm.sup.2 was applied; and wherein 50 cm.sup.2 expanded.

9. A device capable of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a doped buffer layer into an epitaxial device/active layer of claim 8 wherein drift layer carrier lifetime is not reduced; and wherein BPD expansion is prevented at current densities up to 12 kA/cm.sup.2.

Description

DESCRIPTION OF THE DRAWINGS

[0027] The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of the disclosure may be carried out. The illustrated examples, however, are not exhaustive of the many possible embodiments of the disclosure. Other objects, advantages and novel features of the disclosure will be set forth in the following detailed description when considered in conjunction with the drawings.

[0028] FIG. 1 illustrates a growth schedule of double H.sub.2 etch process.

[0029] FIG. 2 illustrates an epitaxial stack of double etch process for the suppression of BPD expansion into epitaxial layers.

[0030] FIG. 3 illustrates UVPL images of double H.sub.2 etch process pre-stressing (left) and after 1000 s at 13 kW/cm.sup.2 (right).

[0031] FIG. 4 illustrates a growth schedule of a hydrogen etch prior to growth, followed by a growth interrupt after the highly doped buffer layer.

[0032] FIG. 5 illustrates an epitaxial stack of the H.sub.2 etch with a growth interrupt process for the suppression of BPD expansion into epitaxial layers.

[0033] FIG. 6 illustrates UVPL images of the H.sub.2 etch with a growth interrupt process pre-stressing (left) and after 1900 s at 13 kW/cm.sup.2 (right) showing no BPDs after stressing.

DETAILED DESCRIPTION OF THE INVENTION

[0034] This disclosure teaches methods and devices for preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer comprising the steps of providing a substrate, etching the substrate and creating a first etch layer, growing a buffer layer on the first etch layer, creating a growth interrupt layer on the first buffer layer or etching the first buffer layer and creating a second etch layer, and growing a drift layer on the second etch layer.

[0035] A novel product is described herein concerning a device capable of preventing basal plane dislocations (BPDs) from expanding from a SiC substrate or a highly doped buffer layer into an epitaxial device/active layer comprising a substrate, a first etch layer on the substrate, a buffer layer on the first etch layer, a second etch layer or a growth interrupt layer on the buffer layer, and a drift layer on the second etch layer or growth interrupt layer.

[0036] Disclosed herein is a method of preventing BPDs from expanding from the SiC substrate or highly doped buffer layer into the epitaxial device/active layer upon device operation or an electron-hole plasma.

[0037] The invention includes a multi-step process. The substrate is SiC, n-type, p-type or SI. The substrate is first etched or annealed prior to epitaxial growth. The etching or annealing takes place in an inert gas, hydrogen or precursors/hydrogen gas mixture or an inert gas/hydrogen mixture or an inert gas/hydrogen/precursor gas mixture with the carrier gas flowing between 1-200 slm at temperatures between 1400-1800 C.

[0038] The pressure ranges from 10-900 mbar. The time of the etch ranges from 1 min-2 hr. Upon completing the etch, a highly doped epitaxial layer is grown for a desired amount of time. This results in a 0.1-20 m thick epitaxial layer.

[0039] The following step is to perform a growth interrupt, while eliminating some or all precursors from the growth chamber. The growth interrupt occurs between growth temperature and room temperature. The sample is removed from the chamber before the next growth step, or left in the chamber.

[0040] The temperature is brought back to growth temperature if different from the growth interrupt temperature, then a highly doped film is grown, followed by a low doped active layer. Alternatively, a buffer layer is grown prior to the low doped active layer.

[0041] Another embodiment is replacing the growth interrupt with a second etch or anneal, using similar conditions to the first etch.

[0042] Herein, we demonstrate a solution to the long-standing problems in the prior art of device degradation.

[0043] Basal plane dislocations (BPDs) have been a problem for SiC high-voltage bipolar devices for many years as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes. In the prior art, upon device operation, the forward voltage drifts and the reverse leakage current increases for these bipolar devices.

[0044] Another problem in the prior art is these BPDs are sourced from the substrate and propagate into the epitaxial layers during epitaxial growth of SiC.

[0045] We demonstrate a method and device to solve these problems.

Example 1

[0046] In one embodiment, a double H.sub.2 etch was performed where the SiC substrate was first brought up to an etch temperature of 1665 C. in 80 slm H.sub.2 and 70 mbar. The sample was held for 50 min under these conditions. Then, the pressure was increased to 100 mbar and reactor temperature was reduced to a growth temperature of 1620 C., at which point, the precursors were ramped over 5 min.

[0047] A highly doped buffer layer was grown for 6 m at 5 m/h, resulting in an electron concentration of 318.sup.18 cm.sup.3.

[0048] The precursors were then stopped, the pressure was changed to 70 mbar and the temperature was raised to 1665 C.

[0049] The sample was etched for 50 min.

[0050] Then, the pressure was increased to 100 mbar and the temperature was decreased again to 1620 C. and precursors were introduced to grow a 0.5 m buffer layer.

[0051] A 15 m drift layer was then grown at 10 m/h with an electron concentration of 510.sup.15 cm.sup.3.

[0052] The precursors were then terminated and the sample was then cooled to room temperature in H.sub.2.

[0053] The growth schedule and epitaxial layer stack for this process is shown in FIG. 1 and FIG. 2, respectively.

[0054] Using this method, BPDs did not expand until a power density of 13 kW/cm.sup.2 was applied, where 50 cm.sup.2 expanded.

[0055] An ultraviolet photoluminescence (UVPL) image is shown in FIG. 3 demonstrating the BPD expansion after applying 13 kW/cm.sup.2.

Example 2

[0056] In another embodiment, a H.sub.2 etch followed by a growth interrupt was performed where the SiC substrate was first brought up to an etch temperature of 1665 C. in 80 slm H.sub.2 and 70 mbar.

[0057] The sample was held for 50 min under these conditions.

[0058] The reactor temperature was reduced to a growth temperature of 1620 C. at which point, the pressure was increased to 100 mbar and the precursors were ramped up over 5 min.

[0059] A highly doped buffer layer was grown for 6 m at 5 m/h, resulting in an electron concentration of 318.sup.18 cm.sup.3.

[0060] The precursors were stopped and the temperature was reduced to 1000 C.

[0061] Upon reaching the growth interrupt temperature, the temperature was then brought back to growth temperature of 1620 C. and precursors were introduced to grow a 0.5 m buffer layer.

[0062] A 15 m drift layer was then grown at 10 m/h with an electron concentration of 510.sup.15 cm.sup.3.

[0063] The precursors were then terminated and the sample was cooled to room temperature in H.sub.2.

[0064] The growth schedule and epitaxial layer stack for this process is shown in FIG. 4 and FIG. 5, respectively.

[0065] Using this process, no BPDs expanded into the epitaxial layer when stressed with a power density of 13 kW/cm.sup.2.

[0066] An ultraviolet photoluminescence (UVPL) image is shown in FIG. 6, demonstrating the BPD expansion after applying 13 kW/cm.sup.2.

Example 3

[0067] In another embodiment, the H.sub.2 etch was replaced with an Ar anneal before growth and the growth interrupt was conducted using Ar gas instead of H.sub.2.

[0068] The growth conditions were similar to the previous embodiments, with the exception of the following.

[0069] The sample was ramped in 5 slm Ar and 200 mbar to 1400 C., at which time the pressure was decreased to 70 mbar and the temperature was raised to 1635 C.

[0070] The sample was annealed in 5 slm Ar and 70 mbar for 50 min.

[0071] The carrier gas of Ar was then switched to 80 slm of H.sub.2 under 100 mbar and then the sample temperature was reduced to a growth temperature of 1620 C.

[0072] A highly doped buffer layer was grown for 6 m at 5 m/h, resulting in an electron concentration of 318.sup.18 cm.sup.3.

[0073] The precursors were terminated and the gas was switched to 5 slm Ar.

[0074] The temperature was reduced to 1000 C. and upon reaching the growth interrupt temperature, the temperature was then brought back to growth temperature of 1620 C. under 200 mbar.

[0075] The carrier gas was switched back to 80 slm H.sub.2 and 100 mbar and precursors were introduced to grow a 0.5 m buffer layer.

[0076] A 15 m drift layer was then grown at 10 m/h with an electron concentration of 510.sup.15 cm.sup.3.

[0077] The precursors were then terminated and the sample was cooled to room temperature in H.sub.2.

[0078] Using this method, BPDs did penetrate the epilayer before exposure of 1000 W/cm.sup.2, but in a low density.

Example 4

[0079] In another embodiment, a thin buffer layer was used along with a growth interrupt.

[0080] Here, conditions were similar to that outlined in the H.sub.2 etch plus growth interrupt. However, the initial buffer layer was 0.4 m thick and the buffer layer after the growth interrupt was 1 m thick.

[0081] All other conditions were the same.

[0082] There was no BPD expansion up to 100 W/cm.sup.2, but the BPDs did expand at 1 kW/cm.sup.2.

Example 5

[0083] In another embodiment, a thin buffer layer and growth interrupt were used.

[0084] Again, the conditions were similar to the H.sub.2 etch plus growth interrupt, but the initial buffer layer was 1 m thick and the follow on buffer layer after the H.sub.2 etch was 0.2 m thick.

[0085] The BPDs did not expand up to 1 kW/cm.sup.2, indicating a thinner buffer layer can be used for this process.

Example 6

[0086] Use of other gases during etching or annealing include but are not limited to: Ar, Ar/H.sub.2. H.sub.2, N.sub.2, precursors, and any mixture thereof.

[0087] The time of the etch ranges from 1 min-2 h.

[0088] The temperature of the etch ranges from 1400-1800 C.

[0089] The pressure ranges from 5-900 mbar.

[0090] Flow of carrier gas ranges from 1-200 slm.

Example 7

[0091] The ramp to growth temperature takes place in H.sub.2, Ar, Ar/H.sub.2, with or without carbon precursor.

[0092] The thickness of the highly doped layer is 0.1-20 m thick.

[0093] The growth interrupt uses similar gases to those in the etching or annealing process.

[0094] The temperature ranges from room temperature to 1800 C.

[0095] The pressure ranges from 5-900 mbar.

[0096] The carrier flow ranges between 1 and 200 slm.

[0097] The sample is removed from the growth chamber during the growth interrupt.

[0098] The time varies from 1 min-2 h.

[0099] The layer after the growth interrupt is unintentionally doped, low doped or highly doped material.

[0100] For the success of bipolar SiC high power devices, SiC epitaxial layers need to be free of basal plane dislocations (BPDs) as they source Shockley-type stacking faults in the presence of an electron-hole plasma and cause forward voltage drifts, leading to device failure. Research has been conducted over the years to mitigate the expansion of BPDs propagating from the substrate into the epitaxial device layers. While these ex-situ and in-situ processes have been extremely successful, limiting the 200-1000 BPD/cm.sup.2 in the substrate from penetrating into the epitaxial layers, the issue remains that under high current densities (>1000 A/cm.sup.2), the injected carrier concentration is sufficiently high to expand the BPDs from the substrate into the epitaxial layer, thus becoming device killers.

[0101] We developed an in-situ growth process that incorporates a H.sub.2 etch prior to the growth of the buffer layer to convert BPDs to electrically benign threading edge dislocations, followed by a growth interrupt between the buffer layer and the drift layer, which significantly quenches the buffer layer lifetime, preventing BPDs from expanding into the drift layer during high current densities.

[0102] Note the drift layer carrier lifetime is not reduced.

[0103] Using our new process, we successfully demonstrated the prevention of BPD expansion at current densities up to 12 kA/cm.sup.2.

[0104] We have also incorporated our novel growth technique to commercially grown, full 150 mm wafers, and investigated its robustness, demonstrating a lab-to-fab transition, its manufacturability and ultimate impact of the novel defect mitigation process.

Advantages and New Features

[0105] 1) The etch or anneal prior to growth is conducted to increase the conversion of BPDs to threading edge dislocations. [0106] 2) This enables a low density of BPDs in the highly doped buffer layer. [0107] 3) The growth interrupt after the buffer layer reduces the carrier lifetime of the material, thus reducing the ability for enough electron-hole recombination energy at the BPDs, including BPD partials, to cause them to expand into Shockley faults, and expand into the epitaxial layer. [0108] 4) Both the H2 etch before growth and the growth interrupt have been patented by us here at the US Naval Research Laboratory. However, this is a new feature with a highly doped buffer layer between them and using the two processes together. [0109] 5) A key difference is that the growth interrupt disclosed herein occurs at a lower temperature of 1000 C., which is key to cause carrier lifetime reduction. [0110] 6) The prior art does not prevent BPD expansion at high current densities. [0111] 7) The prior art did not prevent the expansion of BPDs under high power density stressing or high current densities. [0112] 8) Therefore, it was not known this current method disclosed herein would result in the suppression of BPD expansion under high power densities.

[0113] The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. In addition, although a particular feature of the disclosure may have been illustrated and/or described with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Also, to the extent that the terms including, includes, having, has, with, or variants thereof are used in the detailed description and/or in the claims, such terms are intended to be inclusive in a manner similar to the term comprising.