Method for oxidizing a substrate surface using oxygen

Abstract

A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET.

Claims

1. A method for producing a crystalline oxide layer on an In-containing III-As, III-Sb or III-P compound semiconductor substrate, comprising in vacuum conditions providing an In-containing III-As, III-Sb or III-P substrate having a substrate surface which is clean from amorphous native oxides, and heating said substrate having a clean surface to a temperature of about 250-550° C., and oxidizing it at said temperature of about 250-550° C. by introducing oxygen gas onto the surface of the substrate, wherein said method produces a compound semiconductor substrate comprising at least an In-containing III-As, III-Sb or III-P base material having a first side and a second side, and a crystalline (3×1)-O, c(4×2)-O, (1×2)-O, (2×3)-O, (3×1)-SnO, (3×3)-SnO, or (1×1)-SnO oxide layer being formed on at least a part of the first side of the base material.

2. The method according to claim 1, wherein the In-containing III-As, III-Sb or III-P substrate is made of InAs, InSb, InP, InGaAs or InGaSb.

3. The method according to claim 1, wherein the substrate is cleaned by argon-ion sputtering and post heating in ultra-high-vacuum (UHV) conditions at least to 400° C., or by pure heating in UHV at around 400-550° C.

4. The method according to claim 1, wherein the cleaned substrate is covered by a tin (Sn) layer.

5. The method according to claim 1, wherein the cleaned In-containing III-As substrate is heated to a temperature of about 340-400° C.

6. The method according to claim 1, wherein the cleaned In-containing III-Sb substrate is heated to a temperature of about 340-450° C.

7. The method according to claim 1, wherein the cleaned In-containing III-P substrate is heated to a temperature of about 450-500° C.

8. The method according to claim 1, wherein the heating and the oxidation of the substrate are carried out simultaneously.

9. The method according to claim 1, wherein the substrate is oxidized for 15 to 45 minutes.

10. The method according to claim 9, wherein the substrate is oxidized for 15 to 30 minutes.

11. The method according to claim 1, wherein the oxygen gas pressure is between 5×10.sup.−7 and 5×10.sup.−5 mbar.

Description

DESCRIPTION OF THE DRAWINGS

(1) In the following, the invention will be described in more detail with reference to the appended drawings, in which

(2) FIG. 1 shows a simplified representation of a cross section of a compound semiconductor substrate according to the invention,

(3) FIG. 2 shows LEED patterns from the InAs(100)c(4×2)-O and InAs(100)(3×1)-O layers. The white squares show the (1×1) unit cells of the InAs substrate and the white rectangles show the unit cells of the c(4×2)-O and (3×1)-O layers.

(4) FIGS. 3a, 3b and 3c show (a) an atomic model for the c(8×2) structure of the starting InAs surface, (b) an atomic model for the (3×1)-O layer on InAs, and (c) an atomic model for the c(4×2)-O layer on InAs. The O, In, and As atoms are shown with black, white, and gray spheres, respectively.

(5) FIG. 4 shows valence-band photoemissions from the InAs(100)(3×1)-O and c(4×2)-O layers,

(6) FIG. 5 shows core-level photoemission spectra for In 4d and As 3d lines, and

(7) FIG. 6 shows a simplified cross-sectional view of a structure in semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

(8) FIG. 1 shows a simplified representation of a cross section of a compound semiconductor substrate according to the invention. The substrate comprises In-containing III-As, III-Sb or III-P base material 1 having a first side and a second side, and a crystalline oxide layer 2 being formed on at least a part of the first side of the base material. The base material can be an In-containing III-As, III-Sb or III-P substrate or it can be an In-containing III-As, III-Sb or III-P layer on the surface of a substrate made of some other material, for example silicon (Si). The crystalline oxide layer has a structure of (3×1)-O, (2×3)-O, c(4×2)-O, (1×2)-O, (3×1)-SnO, (3×3)-SnO, or (1×1)-SnO depending on the base material.

(9) Preferably, the crystalline oxide layer 2 is formed on the whole surface of the first side of the base material. The oxide layer can comprise some crystal defects i.e. amorphous regions or other crystalline structures, but preferably at least 90% of the layer comprises said crystalline structure. The valence-band and core-level photoemission results indicate that possible defect concentration is smaller than 5×10.sup.11 defects per cm.sup.2.

(10) In the method for forming a crystalline oxygen-induced In-containing III-As, III-Sb or III-P semiconductor surface, the surfaces of the base material are first cleaned from the amorphous native surface oxides and the carbon combination. The cleaning can be carried out by argon ion sputtering and post heating in an ultrahigh vacuum (UHV) chamber. The argon ion sputtering and post heating in UHV conditions at least to 400° C. leads to well-defined c(8×2) reconstructions on the starting InAs and InSb surfaces and a (2×4) structure on the InP substrate. These starting surfaces can be obtained also by pure heating in UHV at around 400-550° C. or more to remove a protective As-cap layer produced by an epitaxial growth method. In the vacuum conditions, preferably the chamber base pressures lower than 5×10.sup.−8 mbar were used.

(11) Before oxidations, the clean starting surfaces showed (i) sharp c(8×2) or (2×4) low-energy-electron-diffraction (LEED) patterns, (ii) large smooth areas with terraces usually in the order of 100 nm in diameter size as deduced by scanning tunneling microscopy (STM), and (iii) no oxygen and carbon contamination as deduced by x-ray photoelectron spectroscopy (XPS).

(12) In the oxidation process, oxygen is adsorbed on the c(8×2) or (2×4) surface. FIG. 3a shows the InAs surface with an oxygen atom in the energetically most favourable atom position. The stability of this adsorption position, which is located in the second surface layer, i.e. below the surface, is very significant. It is so stable (˜1 eV more stable than the other adsorption positions) because the relatively electronegative oxygen is bound to four relatively electropositive Indium atoms. It is important to note that this kind of adsorption site is found because the peculiar c(8×2) structure includes a mixed (III-V) first surface layer.

(13) A better understanding of the present invention such as oxidation conditions may be obtained through the following examples which are set forth to illustrate, but are not to be construed to limit of the present invention.

(14) The following examples have been carried out using a surface-science system (Omicron) which includes three different vacuum chambers connected via gate valves, so that the samples can be transferred between chambers without breaking the vacuum conditions. The samples were put into the vacuum through the loading chamber. The oxidations were performed in the preparation chamber, and oxidized surfaces were characterized in the analysis chamber. The same surface cleaning and oxide preparations were done also in a separate vacuum system at the MAX-lab using the beamline 41 at the synchrotron ring MAX-I.

(15) Oxidation experiments were performed in a vacuum chamber using molecular oxygen gas with a leak valve via which O.sub.2 gas was injected into the chamber. The O.sub.2 pressure was controlled to be between about 5×10.sup.−7 and 5×10.sup.−5 mbar during oxidation experiments. The sample surface was faced toward the leak valve at a distance of about 15 cm. The oxidation time of the substrates heated simultaneously was about 15-30 minutes. The heating and oxygen exposures were shut down simultaneously after the oxygen exposures. The substrate temperature during the above mentioned oxidation conditions affected the formed crystal structure of the oxidized semiconductor, preferably as follows: The temperature about 340-400° C. produced an InAs(100)(3×1)-O layer The temperature about 400-450° C. produced an InAs(100)c(4×2)-O layer The temperature about 340-450° C. produced an InSb(100)(3×1)-O layer The temperature about 340-450° C. produced an InSb(100)(1×2)-O layer The temperature about 450-550° C. produced an InGaAs(100)c(4×2)-O layer,
which clearly indicates that InGaAs(100)(3×1)-O layer is formed below 550° C. if the amount of Indium is high enough in the surface layer. The calculations predict the formation of InGaAs(100)(3×1)-O when the Indium amount increases in a surface layer of InGaAs. The temperature range in the case of InGaSb is similar as InGaAs.

(16) For the oxide layers including tin (Sn), the substrate temperature during the above mentioned oxidation conditions affected the formed crystal structure of the oxidized semiconductor, preferably as follows: The temperature about 370-400° C. produced an InAs(100)(3×1)-SnO layer The temperature about 400-450° C. produced an InAs(100)(3×3)-SnO layer The temperature about 370-450° C. produced an InP(100)(1×1)-SnO layer The temperature about 450-550° C. produced an GaAs(100)(3×1)-SnO layer.

(17) The examples of the oxidation process of the InAs and InSb substrates are shown on the following Tables 1 and 2. The substrates are heated to the desired temperature before starting the oxidation. The formed crystalline structure of the (3×1)-O layer was detected by the low-energy-electron-diffraction (LEED) measurement. Table 1 presents the oxidation of InAs substrate with the different oxidation times. The oxygen gas pressure was 4×10.sup.−6 mbar during oxidation.

(18) TABLE-US-00001 TABLE 1 Oxidation T (° C.) t (min) LEED I 374 5 c(4x2) II 376 15 (3x1) + weak c(4x2) III 375 20 (3x1) + weak c(4x2) IV 374 30 (3x1) V 373 45 weaker (3x1)

(19) Table 2 presents the oxidation of InSb substrate with the different oxidation times, the oxygen gas pressure was 3-4×10.sup.−6 mbar.

(20) TABLE-US-00002 TABLE 2 Oxidation T (° C.) t (min) LEED I 350 5 (1x2) with splitted x2 spots II 349 10 (1x2) with splitted x2 spots III 353 15 (3x1) + weak (1x2) with splitted x2 spots IV 351 20 (3x1) V 351 30 (3x1)

(21) There is also an alternative embodiment to produce a (3×1)-O layer on the In-containing III-As or III-Sb substrate. Namely, the InAs(100)c(4×2)-O layer was prepared first on the substrate by using a temperature of 400-450° C., and then the substrate was taken out from the vacuum chamber into air where it was kept about 30 min. After that the sample was transferred back into the vacuum conditions and heated to about 400-450° C. for 20 min. That also led to the formation of (3×1)-O. This shows that the starting InAs(100)c(4×2)-O layer can “catalyze” the formation of (3×1)-O since the same air-exposure of clean InAs surface does not produce the (3×1)-O. In FIG. 3c is shown an atomic model for c(4×2)-O layer on InAs structure.

(22) FIG. 2 shows the LEED intensity patterns from the c(4×2)-O and (3×1)-O layers on the InAs substrate. It is worth noting that the pattern from the InSb(100)(3×1)-O layer was similar to that in FIG. 2. First of all, the sharp intensity spots with low background intensity reveal that both oxide layers are well-ordered or crystalline. Second, the additional intensity spots inside the 1×1 unit cell, which is shown with a white square in FIG. 2, reveal that the oxide layer includes (3×1) crystal lattice, which is shown with the white rectangle.

(23) By comparing the different measurements with ab initio calculations, a preliminary atomic model for the crystal structure of (3×1)-O layers is proposed in FIG. 3b.

(24) FIG. 4 shows valence-band photoemissions from the InAs(100)(3×1)-O and c(4×2)-O layers. The measurements show that these interfaces do not include metallic electronic states around the Fermi energy. Moreover, it is important to note that the band bending, which is more sensitive to defects, did not occur as compared to the clean InAs(100)c(8×2), supporting the absence of pinning. These results indicate that the harmful Fermi-level pinning can be avoided in MOSFETs. Also scanning tunneling spectroscopy (STS) measurements show that these crystalline oxide layers do not cause harmful electronic states in the band-gap of InAs. The valence band maximum difference (or offset) between the InAs substrate and the (3×1)-O layer is estimated in FIG. 4 using a difference spectrum between the InAs(100)(3×1)-O and InAs(100)c(4×2)-O spectra, in which the InAs band edge is basically removed. This difference spectrum gives an estimation for the (3×1)-O valence band edge: it has a 1.0-1.4 eV higher binding energy than the InAs one, which might be high enough to provide an energy barrier for electric carriers in the valence band of MOSFETs. For the reference, the Fermi-level emission was measured from an air-exposed InAs(100)c(8×2) surface, which was oxidized and showed a poor (1×1) LEED. That spectrum showed an emission at the Fermi-level, as expected to arise from defect states of such an amorphous surface.

(25) FIG. 5 shows core-level photoelectron spectra for the In 4d and As 3d lines. The features (peaks or shoulders) at the low kinetic energy side demonstrate the presence of oxygen and the formation of the oxide layer.

(26) The interface stability that is an important property for the applications was tested as follows. The passivity of the InAs(100)(3×1)-O and InAs(100)c(4×2)-O surfaces were tested by taking the samples into the atmosphere for 0.5-1 hours. After that they were transferred back into the vacuum chamber and characterized by LEED and STM as a function of the post heating time. After one hour air exposure, the InAs(100)(3×1)-O sample produced, without any post heating, a (3×1) pattern. Naturally, the obtained pattern was weaker than the (3×1) pattern before air exposure, but the pattern became clear (3×1) by heating the substrate to 400° C. for 30 min. These LEED findings are supported by the STM from the InAs(100)(3×1)-O surface after 0.5-hour air exposure and post heating at 400° C. One should note that the same air exposure and post heating procedure of the clean InAs(100)c(8×2) surface led to a poor (1×1) LEED without any clear superstructure. These results indeed show that the InAs(100)(3×1)-O layer is stable against rather strong air and temperature loadings. This is an important property, which allows for example the transfer of the (3×1)-O sample via air into another chamber to grow for example a SiO.sub.2 top insulator layer. The stability also indicates that the (3×1)-O layer does not break during the deposition of a top insulator layer. It is worth noting that the atomic layer deposition (ALD) of the gate insulators on InAs(100) and InGaAs(100) is usually performed at substrate temperatures of 250-350° C., at which the InAs(100)(3×1)-O was clearly stable. The same passivation tests for the InAs(100)c(4×2)-O showed a poor (1×1) after air exposure, but after post heating to about 400° C., a (3×1) LEED appeared. This indicates that the c(4×2)-O structure might “catalyze” the formation of the (3×1) layer since we did not observe the same formation after the air exposure of the clean InAs(100)c(8×2) surface.

(27) The following example describes the oxidation process according to the invention by using the InGaAs substrate.

(28) The surface of the GaAs(100) substrate wafer (about 0.5 mm thick) was cleaned from the carbon contamination and amorphous surface oxides with Ar-ion sputtering and heating in an ultrahigh vacuum (UHV) chamber. During the 30 min raster sputtering, the Ar-gas pressure was 1-3×10.sup.−6 mbar, the sputtering voltage was 0.7 kV and the current 10 mA, and the GaAs substrate temperature was about 400° C. After this sputtering, the GaAs substrate was heated to about 570° C. in a vacuum smaller than 1×10.sup.−9 mbar for 30 min. Six such sputtering-postheating cycles produced a clean and smooth surface, which had the (6×6) structure as deduced by LEED and STM. To prepare an InGaAs surface, 1-2 monolayers (ML) of indium were deposited on the clean GaAs(100)(6×6) substrate surface and the sample was heated to 500-550° C. This produced the InGaAs(100)c(8×2) surface. This clean well-defined InGaAs(100)c(8×2) surface was oxidized, resulting in the c(4×2)-O layer similar to the InAs(100)c(4×2)-O case, as follows: First the substrate temperature was increased to about 550° C. in 15 min in vacuum conditions. Then the leak valve of the oxygen (O.sub.2) gas line, connected to the vacuum chamber, was opened and the oxygen pressure was increased to 3-4×10.sup.−6 mbar. After the 15 min oxidation at the oxygen pressure of 3-4×10.sup.−6 mbar and 550° C. (InGaAs), the heating was closed 10 s before closing the oxygen flow. The c(4×2) crystal structure was determined by LEED. The formation of the c(4×2)-O layer in the InGaAs surface clearly indicates that the (3×1)-O layer forms also in InGaAs, like in the InAs case, if the amount of Indium (In) is increased in the InGaAs surface layer.

(29) On the basis of the preparation conditions of InAs(100)c(4×2)-O and -(3×1)-O, in which the (3×1)-O is always formed at a lower temperature than c(4×2)-O, it can be concluded that the (3×1)-O forms on InGaAs at temperatures lower than 550° C.

(30) The oxidation of the InP substrate has been carried out as is described in the following examples.

(31) The surface of the InP(100) substrate wafer (about 0.5 mm thick) was cleaned from the carbon contamination and amorphous surface oxides with Ar-ion sputtering and heating in ultrahigh vacuum (UHV) chamber. During the 30 minutes raster sputtering, the Ar-gas pressure was 1-3×10.sup.−6 mbar, the sputtering voltage was 0.7 kV and the current 10 mA, and the InP substrate temperature was about 370° C. After the sputtering, the InP substrate was heated to about 470° C. in a vacuum smaller than 1×10.sup.−9 mbar for 30 min. Three such sputtering-postheating cycles produced clean and smooth surface, which had the mixed-dimer (2×4) structure as deduced by LEED and STM. This clean well-defined InP(100)(2×4) surface was oxidized, resulting in the (2×3)-O layer, as follows: first the InP substrate temperature was increased to about 480° C. in 15 min in vacuum conditions. Then the leak valve of the oxygen (O.sub.2) gas line, connected to the vacuum chamber, was opened and the oxygen pressure was increased to 3-4×10.sup.−6 mbar. After the 15 min oxidation at the oxygen pressure of 3-4×10.sup.−6 mbar and the temperature of about 480° C. (InP), the heating was closed 10 s before closing the oxygen flow.

(32) The same (2×3)-O layer was also obtained by the 15 min oxidation at the oxygen pressure of 7-8×10.sup.−7 mbar and the temperature of about 460° C. (InP). The (2×3) crystal structure was determined by LEED and STM. X-ray photoelectron spectroscopy (XPS) revealed three peaks for the O1s emission at 528, 531, and 537 eV binding energies. Also the P 2p emission shows two oxygen-related peaks at 133 and 138 eV.

(33) Table 3 presents other examples of the oxidation of InP substrate. The oxidation of the clean InP(100)(2×4) surface was carried out at about 450° C. by changing the oxidation time (the resistive heating voltage and current were 13.0 V and 2.3 A in all the tests I-V). The oxygen pressure was between 5×10.sup.−7 and 5×10.sup.−5 mbar in all cases. The results in Table 3 indicate that 450° C. is a too low temperature for obtaining pure (2×3)-O. The presence of (2×4) in all the cases indicates the presence of some clean InP(100)(2×4) areas on the surfaces.

(34) TABLE-US-00003 TABLE 3 Oxidation T (° C.) t (min) LEED I 453 5 weaker (2x4) than the clean surface (2x4) II 452 10 weak (2x4) + weak (2x3)-O III 455 15 (2x3)-O + weak (2x4) IV 450 20 (2x3)-O + weak (2x4) V 453 30 (2x3)-O + weak (2x4)

(35) The oxidation of Sn-covered surfaces was performed as follows. After cleaning the InAs substrate surface, as described above, 0.5-2.0 ML of tin was deposited onto the cleaned InAs(100)c(8×2) substrate surface at room temperature. This Sn-covered surface was then heated in vacuum at 350-420° C. for 15-30 min, which provided the Sn-induced (1×2) reconstruction, as deduced by LEED and STM. After that the sample was transferred in the oxidation chamber, and its temperature was risen up to 420° C. Then the oxygen (O.sub.2) gas was introduced into the chamber via the leak valve. The oxidation in 3-4×10.sup.−6 mbar for 10 min produced the InAs(100)(3×3)-SnO surface layer. Decreasing the substrate temperature during the oxidation and/or increasing the oxygen exposure produced the InAs(100)(3×1)-SnO.

(36) The electronic structure of an insulator-semiconductor interface has a significant role in the MOSFET transistor applications. The substrate according to the invention, comprising In-containing III-As, III-Sb or III-P base material and a crystalline oxide layer such as (3×1)-O being formed on the In-containing III-As or III-Sb base material or (2×3)-O being formed on the In-containing III-P base material, can be used in the insulator-semiconductor interface in the MOSFET transistors. The example of structure of the MOSFET transistor comprising a compound semiconductor substrate according to the invention is presented in FIG. 6. It comprises the In-containing III-As, III-Sb or III-P channel layer 1 such as InAs, InGaAs, InSb, InGaSb or III-P, and the crystalline oxide layer 2 formed on the surface of the channel layer. The second insulator layer 3, which can be for example SiO.sub.2 or Al.sub.2O.sub.3, is formed on the surface of the oxide layer. The structure also comprises a gate metal 4, a source contact layer 5, a source metal 6 which can be for example AuGeNi, a drain contact layer 7 and a drain metal 8 like AuGeNi. The crystalline oxide layer according to the invention serves as a barrier layer for electrons and holes in the In-containing channel so that the electric carriers do not leak toward the gate oxide. The crystalline oxide layer acts as an important part of the gate insulator stack.

(37) The invention is not restricted to the examples of the above description, but it can be modified within the scope of the inventive idea presented in the claims.

REFERENCES

(38) [1] H. Ko, K. Takei, R. Kapadia, S. Chuang, H. Fang, P. W. Leu, K. Ganapathi, E. Plis, H. S. Kim, S. Y. Chen, M. Madsen, A. C. Ford, Y. L. Chueh, S. Krishna, S. Salahuddin, and A. Javey A: Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors. Nature Vol. 468: p. 286 (2010). [2] G. Chen, S. B. Visbeck, D. C. Law, and R. F. Hicks: Structure-sensitive oxidation of the indium phosphide (001) surface. Journal of Applied Physics Vol. 91: p. 9362 (2002).