STACK OF LAYERS FOR PROTECTING AGAINST A PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS WITHIN AN INTEGRATED CIRCUIT

Abstract

A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.

Claims

1. A method for protecting an integrated circuit against an electrical conduction assisted by the presence of defects within a dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit, comprising: etching an encapsulation layer formed above a last metallization level of the interconnection part; etching an electrically conducting layer situated above the etched encapsulation layer and intended at least for the formation of contact pads; forming, on the etched electrically conducting layer and on revealed part or parts of the etched encapsulation layer, a stack comprising a non-porous lower passivation layer, an electrically insulating layer and an upper passivation layer; and locally etching the stack so as to reveal the contact pads.

2. The method according to claim 1, wherein the non-porous lower passivation layer exhibits a smaller quantity of porosities than a threshold.

2. The method according to claim 2, wherein the threshold is equal to 5%.

4. The method according to claim 1, wherein a thickness of the lower passivation layer lies between 50 nm and 150 nm.

5. The method according to claim 1, wherein the lower passivation layer comprises a material selected from the group consisting of: silicon nitride SiN and any material of the type Si.sub.xN.sub.y.

6. The method according to claim 1, wherein the upper passivation layer is thicker than the lower passivation layer.

7. The method according to claim 6, wherein the upper passivation layer comprises silicon nitride SiN.

8. An integrated circuit, comprising: a last metallization level of an interconnection part of the integrated circuit; a stack situated above the last metallization level, wherein said stack comprises: a non-porous lower passivation layer, an electrically insulating layer, and an upper passivation layer, etched openings that reveal contact pads of the integrated circuit which are situated above the last metallization level, said stack protecting the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit, that breakdown caused by electrical conduction assisted by the presence of defects within the at least one dielectric region.

9. An integrated circuit, comprising: an interconnection part, an encapsulation layer situated above a last metallization level of the interconnection part, an electrically conducting layer situated above the encapsulation layer and forming contact pads contacting metallic tracks of the last metallization level through the encapsulation layer, and a passivation stack above the electrically conducting layer and above parts of the encapsulation layer, possessing apertures opening out opposite the contact pads and comprising a non-porous lower passivation layer, an electrically insulating layer and an upper passivation layer.

10. The integrated circuit according to claim 9, wherein the non-porous lower passivation layer exhibits a smaller quantity of porosities than a threshold.

11. The integrated circuit according to claim 10, wherein the threshold is equal to 5%.

12. The integrated circuit according to claim 9, wherein the thickness of the lower passivation layer lies between 50 nm and 150 nm.

13. The integrated circuit according to claim 9, wherein the lower passivation layer comprises a material selected from the group consisting of: silicon nitride SiN and any material of the type Si.sub.xN.sub.y.

14. The integrated circuit according to claim 9, wherein the upper passivation layer is thicker than the lower passivation layer.

15. The integrated circuit according to claim 14, wherein the upper passivation layer comprises silicon nitride SiN.

16. The integrated circuit according to claim 9, wherein the interconnection part comprises at least one metallization level possessing electrically conducting elements mutually separated by dielectric regions, and the integrated circuit comprises at least one non-porous dielectric barrier situated between a porous part of at least one dielectric region and at least one of the two electrically conducting elements separated by the at least one dielectric region.

17. A method, comprising: forming an encapsulation layer above a last metallization level of an integrated circuit; depositing and patterning an electrically conductive layer to form a contact pad and form an interconnection part of the integrated circuit over the encapsulation layer that includes at least two electrically conducting elements; depositing a non-porous lower passivation layer directly on said at least two electrically conducting elements and an exposed upper surface of the encapsulation layer; depositing an electrically insulating layer directly on the non-porous lower passivation layer; depositing an upper passivation layer directly on the electrically insulating layer; and locally etching through the upper passivation layer, the electrically insulating layer and the non-porous lower passivation layer to expose a surface of said contact pad.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Other advantages and characteristics of the invention will become apparent on examining the detailed description of wholly non-limiting modes of implementation and embodiments, and the appended drawings in which:

[0044] FIG. 1 schematically illustrates an exemplary integrated circuit of the prior art, and

[0045] FIGS. 2 to 7 schematically illustrate various modes of implementation and embodiments.

DETAILED DESCRIPTION

[0046] In FIG. 1, which illustrates an exemplary integrated circuit IC according to the prior art, the reference RITX designates the interconnection part (BEOL) of the integrated circuit.

[0047] This interconnection part RITX comprises several metallization levels and several levels of vias.

[0048] In this FIG. 1, only the last-but-one metallization level M.sub.n−1 and the last metallization level M.sub.n have been referenced.

[0049] The various metallic tracks, of for example copper, as well as the various vias are shrouded in a dielectric material generally referred to by the person skilled in the art by the acronym IMD (“Inter Metal Dielectric”).

[0050] The reference 8 designates here the dielectric zones shrouding the metallic tracks of the metallization level M.sub.n as well as the metallic tracks of the metallization level M.sub.n−1 and the vias culminating at this metallization level.

[0051] The dielectric material used in these zones 8 is a porous material with low dielectric constant (low K material). By way of example, the material used is carbon doped hydrogenated silicon oxide (SiOCH) having a percentage of porosities of between 20 and 30 and a dielectric constant K equal to 3.

[0052] Each IMD zone 8 is encapsulated between two protection layers 10 parallel to the substrate and intended to protect the metal of the metallic tracks from oxidation. It is for example possible to use silicon carbonitride (SiCN) which makes it possible to protect the copper metallic tracks from oxidation and also avoids the diffusion of copper into the IMD dielectric material.

[0053] The integrated circuit IC also comprises, in a conventional manner, an encapsulation layer CCAP situated above the last metallization level M.sub.n of the interconnection part RITX. This encapsulation layer CCAP is made for example of oxide of TEOS type and is etched locally so as to allow a contact pad PLCT, of for example aluminum, to contact for example the metallic track P.sub.n of the upper metallization level M.sub.n.

[0054] This contact pad PLCT results from the etching of the electrically conducting layer CC, here aluminum, and, as illustrated in this FIG. 1, this layer CC can also serve to create aluminum patterns BLC1, BLC2, for example lines contacting other contact pads, not represented in this figure, and which lines can be used to convey power supply signals or else lines used for other functions, such as for example the formation of a gridwork, incorporated into secure chips.

[0055] The etched layer CC is thereafter covered with an insulating layer CIS, typically oxide of TEOS type deposited by a high density plasma (HDP) which makes it possible in particular to properly plug the gaps between the patterns of the layer CC.

[0056] The integrated circuit IC finally comprises, above the insulating layer CIS, an upper passivation layer CPSS, generally thick, for example of the order of 5500 Ångstroms, which ensures mechanical protection as well as chemical protection of the integrated circuit.

[0057] This stack formed by the insulating layer CIS and the upper passivation layer CPSS is etched so as to make apertures opening out opposite the contact pad(s) PLCT.

[0058] That said, as explained hereinabove, this stack EMPL, and in particular the insulating layer, is an entry point for moisture which will thereafter possibly generate conduction paths in the porous dielectric 8.

[0059] Reference is now made more particularly to FIGS. 2 to 6, which illustrate different steps of a mode of implementation according to the invention making it possible to limit to the maximum, or indeed to eliminate, the ingress of moisture into the chip from the exterior environment.

[0060] In these figures, elements which are analogous or have functions analogous to those described in FIG. 1, have identical references to those which they had in FIG. 1.

[0061] Depicted in FIG. 2 is the electrically conducting layer CC which, after etching, has formed the contact pad PLCT as well as the patterns BLC1 and BLC2.

[0062] Instead of depositing the insulating layer CIS directly, a lower passivation layer CPSI that is less thick than the upper passivation layer CPSS, typically having a thickness of between 50 and 150 nanometers, is firstly deposited (FIG. 3).

[0063] This lower passivation layer CPSI is non-porous, in particular to moisture, and may be for example formed of silicon nitride SiN.

[0064] The insulating layer CIS, for example oxide of TEOS type is deposited thereafter (FIG. 4) and then, as illustrated in FIG. 5, the whole of the upper passivation layer CPSS is covered.

[0065] After etching of the stack EMPL comprising the lower passivation layer CPSI, the insulating layer CIS and the upper passivation layer CPSS, so as to make an aperture OUV opening out opposite the contact pad PLCT, the structure illustrated in FIG. 6 is obtained.

[0066] This structure is therefore distinguished from the prior art illustrated in FIG. 1 by a stack EMPL comprising a dual passivation (lower passivation layer CPSI and upper passivation layer CPSS). Therefore, possible migration of moisture through the insulating layer CIS from the sides of the stack EMPL will be very greatly impeded or indeed blocked by the presence of the non-porous lower passivation layer CPSI.

[0067] It has therefore been made possible to very greatly limit or indeed to eliminate the risk of ingress of moisture into the porous dielectric of the integrated circuit IC from the exterior and this will consequently limit the risk of premature breakdown of this porous dielectric.

[0068] Moreover, this novel method is perfectly compatible with the conventional CMOS methods and requires only the addition of an extra step, namely the deposition of the lower passivation layer CPSI.

[0069] The embodiment illustrated in FIG. 6 can be combined with the embodiment illustrated in FIG. 7 which, as described in the aforementioned French patent application, provides for the use of at least one non-porous dielectric barrier inserted into the porous dielectric region separating two metallic lines.

[0070] FIG. 7 represents an exemplary bottom part of the integrated circuit of FIG. 6.

[0071] More precisely, the integrated circuit IC comprises a semiconductor substrate SB within and on which have been made various components such as transistors, not represented here for the sake of simplification.

[0072] These components as well as the surface of the substrate SB are conventionally covered with a passivation layer 1, for example a silicon dioxide layer.

[0073] The various components are separated from the interconnection part RITX (BEOL) of the integrated circuit by a first dielectric region 2 commonly referred to by the person skilled in the art by the acronym PMD (Pre Metal Dielectric).

[0074] As indicated hereinabove the interconnection part RITX comprises several metallization levels and several levels of vias. In this example, three metallization levels M1, M2 and M3 have been represented associated with two levels of vias V1 and V2.

[0075] In this exemplary embodiment, two metallic tracks or lines L1 and L2 within the metallization level M1 and two metallic tracks L3 and L4 at the level of the second metallization level M2 have been represented.

[0076] In this example, the metallic tracks of the level M3 as well as the vias situated at the level of vias V1 and V2 are situated at other locations of the integrated circuit and are therefore not represented in this figure.

[0077] As indicated previously, the various metallic tracks, of for example copper, and vias, are shrouded in the IMD (Inter Metal Dielectric) dielectric material.

[0078] These dielectric zones IMD are referenced in this FIG. 7 by the references 6, 8 and 11.

[0079] The protection layers (for example silicon carbonitride (SiCN)), parallel to the substrate and encapsulating the zones IMD 6, 8 and 11 are referenced 3, 7, 10 and 12.

[0080] In FIG. 7, it is seen that the interline dielectric region separating the two metallic lines L1 and L2 comprises a porous central part 60, formed here of SiOCH, flanked by two dielectric barriers 4 and 5 respectively situated between the porous central part 60 and the two metallic lines L1 and L2.

[0081] Likewise, the interline dielectric region separating the two lines L3 and L4 comprises a porous central part 800, formed of SiOCH, flanked by two dielectric barriers 90 and 91 respectively situated between the porous central part 800 and the two metallic lines L3 and L4.

[0082] These dielectric barriers 4, 5, 90, 91 are formed of a non-porous dielectric material that is to say exhibiting a percentage of porosities of less than 5.

[0083] In practice, SiCN which exhibits a percentage of of porosities between 2 and 3 is advantageously used as non-porous dielectric barrier.

[0084] Moreover, as seen in FIG. 7, each metallic line, for example the metallic line L4, is itself flanked by two non-porous dielectric barriers, namely the barrier 91 and the barrier 92.

[0085] Furthermore, the lower part of each metallic line is not in contact with a non-porous dielectric barrier so as to allow possible electrical contact with a subjacent via.

[0086] The interline dielectric region separating the metallic lines L3 and L4 is represented in greater detail in the right part of FIG. 1.

[0087] It will be noted that in this right part, the dielectric region has been represented with a trapezoidal shape which is a shape closer to reality since it results from the etching method.

[0088] As explained hereinabove, should moisture and/or ionic contamination be present, and because also of the trapezoidal shape of the dielectric region, the density of traps increases at the interface and the increased presence of the ions at this interface contributes to the creation of a leakage current I (current assisted by defects). That said, the presence of the non-porous dielectric barriers 90 and 91 makes it possible to interrupt the conduction path between the two metallic lines and consequently to very greatly decrease or indeed to eliminate this leakage current I.

[0089] Thus the dual passivation described in particular in conjunction with FIG. 6 makes it possible to limit or indeed to avoid the ingress of moisture into the integrated circuit, and in case of residual moisture, the presence of the non-porous dielectric barriers makes it possible to interrupt the conduction path between the two metallic lines and consequently to very greatly decrease or indeed to eliminate the leakage current I.

[0090] The integrated circuit is thus still more effectively protected against premature breakdown of the interline dielectric regions.