Method for producing interconnections for 3D integrated circuit

Abstract

Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor.

Claims

1. A method for producing one or more connection elements for an integrated circuit comprising: producing one or more sacrificial elements passing through at least one porous layer, the at least one porous layer surmounting a first transistor produced at least partially in a first semi-conductor layer, including forming one or more first openings passing through the at least one porous layer and filling the one or more first openings with a sacrificial material, forming a support on the at least one porous layer, the support including a second semi-conductor layer, wherein at least one second transistor is produced at least partially in the second semi-conductor layer, after producing the sacrificial elements, removing the one or more sacrificial elements using an etching agent of the sacrificial material introduced through the porous layer, and after forming the at least one second transistor, filling the one or more first openings by means of a conductor material so as to form connection elements using one or more second openings made in the support and emerging respectively on at least one of the first openings.

2. The method according to claim 1, wherein the removal of the one or more sacrificial elements is carried out before the step of forming the support.

3. The method according to claim 1, wherein after the forming of the support on the at least one porous layer and prior to the filling of the one or more first openings by the conductor material, performing at least one step of heat treatment at high temperature using a step of laser annealing or thermal annealing.

4. The method according to claim 1, further comprising, after formation of the one or more first openings and prior to the filling of the one or more first openings by means of a sacrificial material: depositing an encapsulation layer lining the bottom and the side walls of the one or more first openings, and removing the encapsulation layer at the bottom of the one or more first openings, the encapsulation layer remaining on the side walls of the one or more first openings.

5. The method according to claim 1, wherein the one or more first openings are formed by etching through a layer of hard mask, the layer of hard mask being conserved during the step of forming the support.

6. The method according to claim 1, further comprising, after filling the one or more first openings by means of the conductor material: making at least one access well in the support revealing the porous layer, removing the material of the at least one porous layer by etching through the access well, and replacing the material of the at least one porous layer by a dielectric material.

7. The method according to claim 1, wherein the conductor material comprises Cu, W or Co.

8. The method according to claim 6, wherein the conductor material is formed by electroless deposition.

9. The method according to claim 1, wherein the sacrificial material is a polymer material.

10. The method according to claim 9, wherein the etching agent comprises a gas or a plasma capable of reacting with the polymer material.

11. The method according to claim 1, wherein the at least one porous layer is formed on an insulator layer covering the first transistor, one or more connection pads pass through the insulator layer, and at least one of the first openings reveals at least one connection pad.

12. The method according to claim 1, wherein at least one of the one or more first openings reveals a region of the first transistor, the method further including, after removal of the sacrificial material and prior to the filling by means of a conductor material, forming a zone of alloy of metal and semi-conductor on the region of the first transistor.

13. The method according to claim 1, wherein forming the porous layer comprises: forming a layer of SiCN; and forming a layer of SiOC on the layer of SiCN.

14. The method according to claim 13, comprising: forming the layer of SiCN to a thickness of about 20 nm; and forming the layer of SiOC to a thickness of about 140 nm.

15. The method according to claim 1, further comprising, after filling the one or more first openings by means of the conductor material: making at least one access well in the support revealing the porous layer, removing the material of the at least one porous layer by etching through the access well, and replacing the material of the at least one porous layer by a dielectric material.

16. A method for producing one or more connection elements for an integrated circuit, comprising: producing one or more sacrificial elements passing through a first porous layer, the first porous layer formed on a first transistor produced at least partially in a first semi-conductor layer, including forming at least one first opening passing through the first porous layer and filling the at least one first opening with a sacrificial material, forming a second porous layer on the first porous layer and the one or more sacrificial elements such that the one or more sacrificial elements are completely surrounded by the first and second porous layers, removing the one or more sacrificial elements using an etching agent capable of being introduced through the first and second porous layers to produce at least one second opening, forming a second semi-conductor layer on the second porous layer, wherein at least one second transistor is formed at least partially in the second semi-conductor layer, forming at least one aperture through the second semi-conductor layer and the second porous layer to expose the at least one second opening, and filling the at least one second opening and the aperture with a conductor material so as to form connection elements.

17. The method according to claim 16, further comprising, after formation of the at least one first opening and prior to the filling of the at least one first opening by means of a sacrificial material: depositing an encapsulation layer lining the bottom and the side walls of the at least one first opening, and removing the encapsulation layer at the bottom of the at least one first opening, the encapsulation layer remaining on the side walls of the at least one first opening.

18. The method according to claim 16, wherein forming at least one of the first and second porous layers comprises: forming a layer of SiCN; and forming a layer of SiOC on the layer of SiCN.

19. The method according to claim 18, comprising: forming the layer of SiCN to a thickness of about 20 nm; and forming the layer of SiOC to a thickness of about 140 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will be better understood on reading the description of embodiment examples given for purely illustrative purposes and in no way limiting, while referring to the appended drawings in which:

(2) FIGS. 1A-1L serve to illustrate an example of method for producing connection elements between different levels of transistors of a 3D integrated circuit in which sacrificial elements are formed in at least one layer of porous material, these sacrificial elements then being replaced by a conductor material;

(3) FIG. 2 illustrates an embodiment variant providing for a protective layer of the porous material;

(4) FIGS. 3A-3C illustrate an embodiment variant providing for an encapsulation layer of the porous material;

(5) FIG. 4 illustrates an embodiment variant of the method providing for a structure for supporting the porous material;

(6) FIGS. 5A-5C illustrate an embodiment variant of the method providing for a replacement of the porous material by a dielectric material;

(7) FIGS. 6A-6B illustrate an embodiment variant of the method in which the sacrificial elements are produced in localised regions intended to receive a conductor material sensitive to a considerable thermal budget, between two levels of transistors of the 3D circuit;

(8) FIGS. 7A-7B illustrate an embodiment variant in which a silicidation of regions of transistors belonging to different levels is carried out at the same time.

(9) Identical, similar or equivalent parts of the different figures bear the same numerical references so as to make it easier to go from one figure to the next.

(10) The different parts in the figures are not necessarily shown according to a uniform scale in order to make the figures more legible.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

(11) An example of method for producing connection elements for a 3-dimensional or “3D” integrated circuit device will now be given in conjunction with FIGS. 1A-1L.

(12) The device may be produced from a substrate 1 of semi-conductor on insulator type, for example of SOI type (SOI for “Silicon on Insulator”), including a semi-conductor support layer 10, an insulator layer 11 lying on the support layer 10, and a superficial semi-conductor layer 12 in which channels of transistors T.sub.11 and transistor T.sub.12 are provided. The transistors T.sub.11 and T.sub.12 may be MOS transistors (MOS for Metal Oxide Semi-conductor) produced for example according to a technology of FDSOI (Fully Depleted Silicon On Insulator) type. In this example, the transistors T.sub.11 and transistor T.sub.12 belong to a first level N.sub.1 of a stack of electronic components spread out over 3 dimensions.

(13) The transistors T.sub.11, T.sub.12 formed on the substrate 1 comprise a source region 13, a drain region 14, as well as a channel region 16, connecting the source region 13 and the drain region 14, a gate dielectric 17 and a gate 18 on the zone 17 of gate dielectric. Insulator spacers 19 are also produced on either side of the gate 18.

(14) In this embodiment example, regions of transistors T.sub.11, T.sub.12, in particular source, drain and gate regions, are surmounted respectively by zones 23 of alloy of metal and semi-conductor commonly called silicidation zones to form contacts.

(15) The transistors T.sub.11, T.sub.12 are covered with at least one layer 33 of dielectric material, for example at least one layer of SiO.sub.2, which can then be planarized for example by chemical mechanical planarization (CMP).

(16) The first holes 41, 42, 43, 44, 48 are then produced in the dielectric layer 33 which are intended to receive pads making it possible to produce contact points on the transistors T.sub.11, T.sub.12 (FIG. 1A).

(17) A filling of the first holes 41, 42, 43, 44, 48 is then carried out by means of a sacrificial material 51, intended to be removed later (FIG. 1B). This sacrificial material 51 may be a polymer material, for example such as polyamide or PMMA (polymethyl methacrylate) or a fluorinated polymer or a synthetic resin.

(18) Then, at least one porous layer 60 is formed on the dielectric layer 33 (FIG. 1C).

(19) The porous layer 60 may be formed of a stack including a layer 61 based on a first porous material such as for example SiCN of thickness for example of the order of 20 nm and a layer 62 based on a second porous material, in particular a material of “ultra low-k” type such as for example SiOC of thickness for example of the order of 140 nm.

(20) Then, one or more second holes 63, 64, 65, 66 are produced in this porous layer 60. The second holes 63, 64, 65, 66 communicate respectively with one or more of the first holes 41, 42, 43, 44, 48 filled with sacrificial material 51.

(21) The second holes 63, 64, 65, 66 may be produced by etching of the porous layer 60 through a hard mask 70. This hard mask 70 may be formed of a stack including a layer 71 for example based on TEOS (tetraethyl orthosilicate) surmounted by another layer 72 for example based on TiN of the order of 15 nm (FIG. 1D).

(22) The second holes 63, 64, 65, 66 are then filled with a sacrificial material, advantageously the same sacrificial material 51 as that filling the first holes 41, 42, 43, 44, 48 (FIG. 1E). A step of planarization (CMP) may be carried out after filling in order to remove excess sacrificial material 51.

(23) In a variant of the steps described in conjunction with FIGS. 1A to 1E, it is possible to carry out a method according to an approach of type known as “Dual Damascene” for which, the first holes 41, 42, 43, 44, 48, the second holes 63, 64, 65, 66 are filled at one time.

(24) It is then possible to reiterate one or more times a sequencing of steps such as described previously and consisting in forming a porous layer 60 and a hard mask 70 on this porous layer 60, then forming holes in the porous layer 60 and filling these holes by means of a sacrificial material 51.

(25) It is thus possible to obtain a structure such as illustrated in FIG. 1F comprising elements 69 based on sacrificial material 51 arranged in openings passing through at least one porous layer 60 formed on the transistors T.sub.11, T.sub.12.

(26) An additional sacrificial porous layer 60′ may then be formed, so as to cover the elements 69 based on sacrificial material 51 and the other porous layers 60.

(27) A removal is then carried out of the sacrificial elements 69 using an etching agent 80 capable of being introduced through the porous layer(s) 60′, 60 (FIG. 1G). This etching agent 80 is preferably gaseous or in the form of plasma in order to facilitate its elimination once the etching is carried out. In the case of a sacrificial material 51 based on polymer material, the etching agent 80 is for example oxygen or a plasma based on oxygen or supercritical CO.sub.2.

(28) The set of first holes 41, 42, 43, 44, 48 and second holes 63, 64, 65, 66 emptied of sacrificial material form openings 68 through the porous layer(s) 60, 60′ and extending in this example up to the contact zones 23 of the transistors T11, T12 (FIG. 1H).

(29) The stack of porous layers 60, 60′ may be then covered with another layer, for example a layer 91 of dielectric material such as SiO.sub.2, intended to serve as bonding layer to produce an assembly with a support.

(30) Onto this layer 91 of dielectric material is then transferred, for example by molecular bonding, a support including a semi-conductor layer 112 (FIG. 1I). This support 100 may be equipped with an insulator layer 111, for example based on SiO.sub.2, which is placed in contact with the dielectric layer 91 to carry out the bonding. According to a variant (not represented), it is possible to transfer a semi-conductor layer 112 directly onto the dielectric layer 91.

(31) Then, at least one transistor T.sub.21 of a second level N.sub.2 of the 3D stack is formed from the semi-conductor layer 112. The transistor T.sub.21 produced has a channel region which extends into the semi-conductor layer 112, source and drain regions which may be at least partially formed in the semi-conductor layer 112, as well as a gate dielectric and a gate formed on the channel region.

(32) The formation of the transistor T.sub.21 may include a step of activation of dopants by means of at least one thermal annealing, in particular at high temperature. High temperature is here taken to mean a temperature above 500° C. This thermal annealing may be carried out by means of a laser L for example at a localised temperature of the order of 1200° C., which makes it possible to implement a very localised annealing (FIG. 1J).

(33) During such a step, the porous layers 60, 60′ may advantageously play the role of thermal insulator and thereby limit the diffusion of heat towards the transistors T.sub.11, T.sub.12 of lower level N.sub.1.

(34) Then, a passivation insulator layer 121 is formed, for example based on SiO.sub.2 on the transistor T.sub.21 of the second level N.sub.2.

(35) Openings 133, 134, 135, 136 are then made in this insulator layer 121.

(36) Certain openings 133, 136 pass through the insulator layer 111 of the support 100 and emerge on the openings 68 made in the stack of porous layers 60, whereas other openings 134, 135, may emerge on regions of the transistor T.sub.21, for example respectively on gate region, source region and drain region (FIG. 1K). The openings 133, 134, 135, 136 may be produced at the same time or in a variant successively by groups. It is possible for example to produce the openings 133, 136 passing through the insulator layer 111 of the support 100 and emerging on the openings 68 then producing the other openings 134, 135, emerging on regions of the transistor T.sub.21.

(37) The openings 133, 134, 135, 136 are then filled with conductor material 141 (FIG. 1L). This conductor material 141 may be a metal such as for example copper. In a variant, the conductor material 141 may be formed by an organometallic material such as described for example in the document: “Metallopolymers with emerging applications”, of Eloi et al., Materials Today, April 2008, or by an organometallic material capable of being transformed into metal for example such as that described in the document “Metal deposition by electron beam exposure of an organometallic film”, of Craighead et al., American Institute of Physics, 1986. According to another variant, the filling of the openings by a metal conductor material may be carried out by means of a method such as described for example in the document FR 3002688.

(38) The sizes of the openings 133 and 136 are determined by those skilled in the art in order to be able to be filled, potentially integrally. It is also possible to deposit, prior to filling by the material 141 in the openings, a diffusion barrier based for example on Ta/TaN.

(39) Connection elements 150 are thereby produced between superimposed levels N.sub.1 and N.sub.2 of a 3D circuit without having subjected these connection elements 150 to a too high thermal budget and capable of deteriorating the interconnection structure and in particular the conductor material 141 based on which this structure is formed.

(40) A variant of the example of method which has been described provides, after the step described in conjunction with FIG. 1C and consisting in making the holes 63, 64, 65, 66 in the porous layer 60, for conserving at least one layer 71 forming the hard mask 70 (FIG. 2). This layer 71 may be for example based on low temperature silicon oxide or silicon nitride, or for example based on a low-k material of BN/SiCBN type resistant to considerable thermal budgets. This hard mask layer 71 then serves especially as a layer for protecting the porous material from subsequent etching step(s). At the step described previously in conjunction with FIG. 1L where the connection elements 150 are produced, this protective layer 71 may be conserved.

(41) Another variant, which may be combined with the preceding variant, provides for, after having made the holes 63, 64, 65, 66 in the porous layer 60, forming an encapsulation layer 81 lining the bottom and the side walls of the holes 63, 64, 65, 66 (FIG. 3A). The thickness of this layer 81 may be provided as a function of the width I of the holes 63, 64, 65, 66, for example of the order of ⅓ the width I of the holes. This encapsulation layer 81 may be for example based on silicon nitride and of thickness for example of the order of 10 nm.

(42) Then a removal of the encapsulation layer 81 at the bottom of the holes 63, 64, 65, 66 is carried out, the encapsulation layer being conserved at the level of the side walls of the holes 63, 64, 65, 66 (FIG. 3B). This removal may be carried out for example by means of a plasma etching method. The encapsulation layer 81 then serves as a lateral protection of the porous material. The encapsulation layer 81 is also intended to serve to produce a mechanical resistance of the layers during steps of heat treatment during the production of an upper stage.

(43) The holes 63, 64, 65, 66 are then filled by the sacrificial material 51 (FIG. 3C).

(44) It is then possible to reiterate the sequence of steps described previously in conjunction with FIGS. 2, 3A, 3B, 3C, in order to form several levels of porous layers 60 with at each level a protective layer 71 and an encapsulation layer 81 (FIG. 4).

(45) The set of protective layer(s) 71 and encapsulation layer(s) 81 can also make it possible to assure the cohesion of the stack of porous layers 60 especially during steps of heat treatment and/or during the removal of the sacrificial material 51 and/or during a potential step of replacement of the porous material.

(46) According to an embodiment variant (FIGS. 5A-5C), once the connection elements 150 are produced, it is provided to replace the porous layer(s) 60 by another dielectric material.

(47) To do so, at least one access well 155 is produced passing through the insulator layer 121, and which reveals the porous layer 60 or the stack of porous layers 60 (FIG. 5A).

(48) Then the porous material(s) are removed by etching through the access well 155 (FIG. 5B). This etching may be carried out for example by means of a gaseous mixture comprising a fluorinated gas such as for example CHF.sub.3 to remove a material based on SiCN or C.sub.4F.sub.8 to remove a porous material based on SiOC, the fluorinated gas being mixed with a neutral gas such as N.sub.2 or Ar.

(49) Then, the porous material(s) are replaced by a dielectric material 160 which may itself be porous. The replacement dielectric material 160 may be for example SiO.sub.2 or for example of “low-k” type such as SiCBN, or SiOCH, or BN or “ultra low-k” type such as SiOC (FIG. 5C).

(50) This variant makes it possible to have in the end a dielectric material 160 between the levels N.sub.1 and N.sub.2 of the integrated circuit which has not undergone transformation and has not been degraded by the steps of the method described previously.

(51) According to another implementation variant of one or the other of the examples of methods for producing inter-level connection elements described previously, a sacrificial material 51 and a replacement of this sacrificial material is provided on certain localised regions of the stack situated between the levels N.sub.1 and N.sub.2 of the 3D stack of components. Localised regions of the stack intended to comprise a material sensitive to certain thermal treatments, for example such as copper, are here targeted.

(52) Thus, according to an example of embodiment of this variant illustrated in FIGS. 6A-6B, the first holes 41, 42, 43, 44, 48 may be directly filled with a metallic material 53 capable of resisting a considerable thermal budget such as for example tungsten. Contact plots 55 are then formed for the transistors T.sub.11, T.sub.12. Then, the elements 69 based on sacrificial material 51 are produced in at least one porous layer 60 (FIG. 6A).

(53) This sacrificial material 51 is then replaced by a conductor material 141 such as copper, less resistant than the metallic material 53 to considerable thermal budgets (FIG. 6B). The replacement is carried out for example by means of a method such as described previously in conjunction with FIGS. 1G-1L.

(54) Another embodiment variant (FIGS. 7A-7B) of one or the other of the examples of methods described previously provides for deferring the silicidation of regions of transistors T.sub.11, T.sub.12 of the first level N.sub.1, and carrying out this step before carrying out a step of filling the openings 133, 134, 135, 136 as described previously in conjunction with FIG. 1L.

(55) In this case, after having formed the openings 133, 134, 135, 136 (FIG. 7A) certain openings 133, 136 communicating with one or more openings 68 passing through the porous layer(s) 60 and emerging respectively on given regions 21a, 21b, 21c, 21d, 21e of the transistors T.sub.11, T.sub.12 of the first level N.sub.1 are used to produce zones of alloy of metal and semi-conductor on these regions. The openings 134, 135 revealing regions 121a, 121b of the transistor T.sub.21 of the second level N.sub.2 are also used to produce zones of alloy of metal and semi-conductor. It is thus possible to produce at the same time zones of alloy of metal and semi-conductor 23, on regions of transistors T.sub.11, T.sub.12 of the first level N.sub.1 and zones of alloy of metal and semi-conductor 123, on regions of the transistor T.sub.21 of the second level N.sub.2 (FIG. 7B). The zones of alloy may be formed by what is commonly known as “electroless” deposition of a metal such as for example Ni or an alloy. Such a method makes it possible to deposit metals at low cost on surfaces or inside complex structures. The metal not having reacted by chemical means may be potentially conserved. In a variant, the zones of alloy may be formed by means of a method such as described for example in the document FR 3002688.