SLAVE DEVICE IDENTIFICATION ON A SINGLE WIRE COMMUNICATIONS BUS

Abstract

A system includes a single wire communications bus, a first slave device, and a second slave device. The first slave device and the second slave device each include a plurality of pins. The first slave device and the second slave device are uniquely identified on the single wire communications bus based on which one of the plurality of pins is coupled to the single wire communications bus.

Claims

1. A system comprising: a single wire communications bus; and a first slave device and a second slave device each comprising a plurality of pins, wherein the first slave device and the second slave device are uniquely identified on the single wire communications bus based on which one of the plurality of pins is coupled to the single wire communications bus.

2. The system of claim 1 wherein the single wire communications bus is coupled to different ones of the plurality of pins on the first slave device and the second slave device.

3. The system of claim 2 wherein the first slave device and the second slave device are associated with the same unique slave identifier.

4. The system of claim 3 wherein the first slave device and the second slave device are uniquely identified based on a register address acted on by a message provided on the single wire communications bus.

5. The system of claim 4 wherein a register address associated with the first slave device and a register address associated with the second slave device are based on which one of the plurality of pins is coupled to the single wire communications bus.

6. The system of claim 5 wherein the first slave device and the second slave device are configured to respond to a message on the single wire communications bus that acts on a register address associated with the slave device.

7. The system of claim 1 wherein the first slave device and the second slave device are uniquely identified based on which one of the plurality of pins is coupled to the single wire communications bus and an impedance coupled to a different one of the plurality of pins.

8. A slave device comprising: a plurality of pins; communications circuitry configured to communicate with one or more other devices via a single wire communications bus; and identification resolution circuitry configured to uniquely identify the slave device on the single wire communications bus based on which one of the plurality of pins is connected to the single wire communications bus.

9. The slave device of claim 8 wherein the slave device has the same unique slave identifier as at least one other slave device coupled to the single wire communications bus.

10. The slave device of claim 9 wherein the slave device is uniquely identified based on a register address acted on by a message provided on the single wire communications bus.

11. The slave device of claim 10 wherein the register address associated with the slave device is based on which one of the plurality of pins is coupled to the single wire communications bus.

12. The slave device of claim 11 wherein the communications circuitry is further configured to respond to a message on the single wire communications bus that acts on the register address associated with the slave device.

13. The slave device of claim 8 wherein the identification resolution is configured to uniquely identify the slave device on the single wire communications bus based on which one of the plurality of pins is coupled to the single wire communications bus and an impedance coupled to a different one of the pins.

14. A method comprising: coupling a plurality of slave devices to a single wire communications bus, each one of the plurality of slave devices comprising a plurality of pins; and uniquely identifying the plurality of slave devices on the single wire communications bus based on which one of the plurality of pins is coupled to the single wire communications bus.

15. The method of claim 14 wherein the single wire communications bus is coupled to different ones of the plurality of pins on at least two of the plurality of slave devices.

16. The method of claim 15 wherein the at least two of the plurality of slave devices have the same unique slave identifier.

17. The method of claim 16 wherein the at least two of the plurality of slave devices are identified based on a register address acted on by a message provided on the single wire communications bus.

18. The method of claim 17 wherein a register address associated with the at least two of the plurality of slave devices is based on which one of the plurality of pins is coupled to the single wire communications bus.

19. The method of claim 18 wherein the plurality of slave devices are configured to respond to a message on the single wire communications bus that acts on a register address associated with the slave device.

20. The method of claim 14 wherein the plurality of slave devices are uniquely identified based on which one of the plurality of pins is coupled to the single wire communications bus and an impedance coupled to a different one of the plurality of pins.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0019] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0020] FIG. 1 is a functional schematic illustrating a conventional single wire communications system.

[0021] FIG. 2 is a diagram illustrating a message for a single wire communications system.

[0022] FIG. 3 is a diagram illustrating a register map for a single wire communications system.

[0023] FIG. 4 is a register map illustrating a register map for a single wire communications system.

[0024] FIG. 5 is a functional schematic illustrating a single wire communications system according to one embodiment of the present disclosure.

[0025] FIG. 6 is a functional schematic of identification resolution circuitry for a single wire communications system according to one embodiment of the present disclosure.

[0026] FIG. 7 is a functional schematic illustrating a single wire communications system according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

[0027] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0028] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0029] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0030] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0033] FIG. 5 illustrates a single wire communications system 40 according to one embodiment of the present disclosure. The single wire communications system 40 includes a first single wire communications bus 42A and a second single wire communications bus 42B. A master controller 44 is coupled to each one of the first single wire communications bus 42A and the second single wire communications bus 42B. A number of slave devices 46 are each coupled to one of the first single wire communications bus 42A and the second single wire communications bus 42B.

[0034] The master controller 44 includes communications circuitry 48, a first-in-first-out (FIFO) buffer 50, a digitally controlled oscillator 52, power management circuitry 54, and secondary communications circuitry 56. The communications circuitry 48 is configured to interface with the first single wire communications bus 42A and the second single wire communications bus 42B in order to facilitate communication with the slave devices 46. The FIFO buffer 50 is used to store and access data required for communication on the first single wire communications bus 42A and the second single wire communications bus 42B. The digitally controlled oscillator 52 is used to generate signals for communication on the first single wire communications bus 42A and the second single wire communications bus 42B. The power management circuitry 54 is responsible for meeting the required power needs of the other circuitry in the master controller 44. The secondary communications circuitry 56 is configured to communicate with one or more other devices on a different type of communication bus, thereby enabling the slave devices 46 to communicate with devices that are not on the first single wire communications bus 42A and the second single wire communications bus 42B. For example, the secondary communications circuitry 56 may be radio frequency front end (RFFE) communications bus circuitry that allows the master controller 44 and thus the slave devices 46 to communicate with one or more other devices on an RFFE communications bus.

[0035] Each one of the slave devices 46 includes power management circuitry 58, communications circuitry 60, functional circuitry 62, a first pin 64A, a second pin 64B, and identification resolution circuitry 66. The power management circuitry 58 is responsible for meeting the required power needs of the other circuitry in the slave device 46. The communications circuitry 60 is configured to facilitate communications on the single wire communications bus 42. The functional circuitry 62 is configured to perform some function, which may be regulated or otherwise controlled by communication over the single wire communications bus 42. In one exemplary embodiment, the functional circuitry 62 includes a radio frequency (RF) switch that may be opened and/or closed in response to commands on the single wire communications bus 42. The first pin 64A is used to connect to one of the single wire communications bus 42 and ground via a power management capacitor C.sub.PM. The second pin 64B is used to connect to the other one of the single wire communications bus 42 and ground via the power management capacitor C.sub.PM. That is, the single wire communications bus 42 may connect to one of the first pin 64A and the second pin 64B. The identification resolution circuitry 66 is configured to uniquely identify the slave device 46 on the single wire communications bus 42 based on which one of the first pin 64A and the second pin 64B is connected to the single wire communications bus 42.

[0036] The identification resolution circuitry 66 may change a USID of the slave device 46, may change a product ID of the slave device 46, may change a register address associated with the slave device 46, or may change any other unique identifier of the slave device 46 based on which one of the first pin 64A and the second pin 64B is connected to the single wire communications bus 42. If the first pin 64A is connected to the single wire communications bus 42, the slave device 46 may be associated with a first USID, while if the second pin 64B is connected to the single wire communications bus 42 the slave device 46 may be associated with a second USID. Similarly, if the first pin 64A is connected to the single wire communications bus 42 the slave device 46 may be associated with a first register address while if the second pin 64B is coupled to the single wire communications bus 42 the slave device 46 may be associated with a second register address. In short, any number of different ways of identifying the slave device 46 may be changed based on the pin 64 coupled to the single wire communications bus 42.

[0037] Using the identification resolution circuitry 66 and changing the pin 64 connected to the single wire communications bus 42 may reduce the number of required slave device 46 parts, thus reducing the number of product lines required to be manufactured, inventoried, and installed. Table 1 illustrates how eight slave devices 46 illustrated in FIG. 5 can be uniquely identified using only two slave device 46 parts:

TABLE-US-00001 Asso- ciated USID address used Part No. First pin Second pin 0x00 0001 QM18x00 Comm. Bus C.sub.PM 0x01 0001 QM18x00 C.sub.PM Comm. Bus 0x02 0001 QM18x01 Comm. Bus C.sub.PM 0x03 0001 QM18x01 C.sub.PM Comm. Bus 0x04 0010 QM18x00 Comm. Bus C.sub.PM 0x05 0010 QM18x00 C.sub.PM Comm. Bus 0x06 0010 QM18x01 Comm. Bus C.sub.PM 0x07 0010 QM18x01 C.sub.PM Comm. Bus
The slave devices 46 may include register maps similar to those discussed above with respect to FIG. 4. Accordingly, the slave devices 46 may respond to two USIDs and change their associated register address based on which USID is used to address them. In addition, the slave devices 46 may change their associated register address based on which one of the first pin 64A and the second pin 64B is coupled to the single wire communications bus 42 to achieve the different associated register addresses shown in the table. Accordingly, all of the slave devices 46 are made the exact same except for the different part numbers thereof, which are hard-coded. This means that eight slave devices 46 may be uniquely addressed using only two slave device 46 parts.

[0038] FIG. 6 shows details of the identification resolution circuitry 66 according to one embodiment of the present disclosure. For context, the first pin 64A and the second pin 64B are shown. The identification resolution circuitry 66 includes a first Schmitt trigger T.sub.SCH1 coupled between the first pin 64A and a digital controller 68 and a second Schmitt trigger T.sub.SCH2 coupled between the second pin 64B and the digital controller 68. A first diode D.sub.1 is coupled between the first pin 64A and the digital controller 68. A first switch SW.sub.1 is coupled in series with a first resistor R.sub.1 between the first pin 64A and the second pin 64B. A second switch SW.sub.2 is coupled in parallel with the first switch SW.sub.1 and the first resistor R.sub.1. A third switch SW.sub.3 is coupled between the first pin 64A and a control node N.sub.C. A fourth switch SW.sub.4 is coupled between the second pin 64B and the control node N.sub.C. A first capacitor C.sub.1 is coupled between the first pin 64A and ground. A second capacitor C.sub.2 is coupled between the second pin 64B and ground. A second diode D.sub.2 is coupled in series with a second resistor R.sub.2 and a power-on-reset (POR) circuit 70 between the second pin 64B and the digital controller 68. A third capacitor C.sub.3 is coupled to ground between the POR circuit 70 and the second resistor R.sub.2.

[0039] In operation, the single wire communications bus 42 is connected to one of the first pin 64A and the second pin 64B, while the supply capacitor C.sub.S is coupled to the other one of the first pin 64A and the second pin 64B. Initially, each one of the first switch SW.sub.1, the second switch SW.sub.2, the third switch SW.sub.3, and the fourth switch SW.sub.4 are open. When the single wire communications bus 42 is turned on, power is applied to the pin 64 connected thereto and delivered via the second resistor R.sub.2 and the third capacitor C.sub.3 to the POR circuit 70, which powers on the digital controller 68 after a delay set by the resistance of the second resistor R.sub.2 and the third capacitor C.sub.3. This is to ensure that the digital controller 68 is not powered on before adequate power is available from the single wire communications bus 42.

[0040] Once the digital controller 68 is powered on, the first switch SW.sub.1 is closed so that the supply capacitor C.sub.S is charged by the single wire communications bus 42. The typical charging time of the supply capacitor S.sub.C is ˜100 μs (5×RC) where R=200 and C=0.1 μF. An initialization time from when the single wire communications bus 42 is turned on is thus assumed to be about 200 μs due to the specification thereof. When a message is sent on the single wire communications bus 42, the pin 64 connected thereto is pulled low. The digital controller 68 detects this within a few nanoseconds via one of the first Schmitt trigger T.sub.SCH1 and the second Schmitt trigger T.sub.SCH2. The digital controller 68 then knows which one of the first pin 64A and the second pin 64B is connected to the single wire communications bus 42. The first switch SW.sub.1 is then opened to prevent the supply capacitor C.sub.S from discharging back through the first resistor R.sub.1, and can close one of the third switch SW.sub.3 and the fourth switch SW.sub.4 to connect the single wire communications bus 42 to the control node N.sub.C which may be connected, for example, to the communications circuitry 48 and thus provide the message. The digital controller may close the second switch SW.sub.2 along with one of the third switch SW.sub.3 or the fourth switch SW.sub.4, depending on which one of the first pin 64A and the second pin 64B is coupled to the single wire communications bus 42, during a fast charge portion of the message (see FIG. 2 above) in order to quickly charge the supply capacitor C.sub.S and one or more other components.

[0041] Notably, the identification resolution circuitry 66 shown in FIG. 6 is merely exemplary. Those skilled in the art will recognize that there are any number of ways to detect which pin the single wire communications bus 42 is connected to and act accordingly, all of which are contemplated herein.

[0042] The concepts discussed above may be extended by adding additional pins to the slave devices 46, as shown in FIG. 7. Here, the slave devices 46 include a third pin 64C, which may be coupled directly to ground or coupled to ground via the supply capacitor C.sub.S. The two extra states afforded by the third pin 64C may further reduce the number of slave device 46 parts required for a given system, as indicated in Table 2:

TABLE-US-00002 Asso- ciated USID address used Part No. First pin Second pin Third pin 0x00 0001 QM18x00 Comm. Bus C.sub.PM Ground 0x01 0001 QM18x00 C.sub.PM Comm. Bus Ground 0x02 0001 QM18x00 Comm. Bus C.sub.PM C.sub.PM 0x03 0001 QM18x00 C.sub.PM Comm. Bus C.sub.PM
As shown, four uniquely addressable slave devices 46 may be achieved by one slave device 46 part when connecting the pins 64 as shown. Table 3 extends this concept using multiple register addressing as discussed above with respect to FIG. 4:

TABLE-US-00003 Asso- ciated USID address used Part No. First pin Second pin Third pin 0x00 0001 QM18x00 Comm. Bus C.sub.PM Ground 0x01 0001 QM18x00 C.sub.PM Comm. Bus Ground 0x02 0001 QM18x00 Comm. Bus C.sub.PM C.sub.PM 0x03 0001 QM18x00 C.sub.PM Comm. Bus C.sub.PM 0x04 0010 QM18x00 Comm. Bus C.sub.PM Ground 0x05 0010 QM18x00 C.sub.PM Comm. Bus Ground 0x06 0010 QM18x00 Comm. Bus C.sub.PM C.sub.PM 0x07 0010 QM18x00 C.sub.PM Comm. Bus C.sub.PM
As shown, eight uniquely addressable slave devices 46 may be achieved by one slave device 46 part when connecting the pins 64 as shown and allowing each slave device 46 to respond to different register addresses based on the USID used to address the slave device 46. Adding additional pins may further increase the number of uniquely addressable slave devices 46 from a single slave device 46 part.

[0043] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.