A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.

A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including receiving a request to sequentially write data to a block of a memory device, in response to receiving the request, writing the data to the block to obtain sequentially written data, initiating accumulation of logical-to-physical (L2P) mapping data corresponding to the sequentially written data, determining that a criterion for terminating the accumulation of the L2P mapping data is satisfied, in response to determining that the criterion is satisfied, terminating the accumulation of the L2P mapping data to obtain accumulated L2P mapping data, and updating an L2P mapping data structure based on the accumulated L2P mapping data.

A host includes: an index tree storing an index including information for identifying a versioning key; and an index update buffer storing a write key included in data subject to a write request and the versioning key corresponding to the write key. When a preset update condition is satisfied, the host transfers the versioning key stored in the index update buffer to the index tree, and when the index update buffer requires recovery, the host designates a recovery section of memory of the storage device including data corresponding to the versioning key which has not been updated to the index tree, to be read by a plurality of threads, reads data included in the recovery section from the storage device through the plurality of threads, and inserts the read data into the index update buffer to recover the index update buffer.

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.

Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.

Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

A Near Memory Processing (NMP) module including: a plurality of memory units: an Input/Output (I/O) interface configured to receive commands from a host system, wherein the host system includes a host memory controller configured to access the plurality of memory units: a decoder configured to decode the commands and generate a trigger; and an NMP memory controller configured to: receive the trigger from the decoder; and generate a signal in response to the trigger to synchronize the NMP module with the host system.

A system including a baseboard management controller (BMC) and a socket is described. The BMC is configured to provide a management interface to a network device. The socket is configured to accept an edge connector of a removable storage card. The BMC is configured to access via the socket at least a portion of the firmware of the BMC stored on the removable storage card.

A system, apparatus and product comprising: a multi-tenant layer that comprises shared resources, wherein the shared resources are accessible to multiple tenants of the storage system, wherein the shared resources comprise shared logic resources and shared data resources; and multiple single-tenant layers, wherein each single-tenant layer is associated with a respective tenant of the multiple tenants, wherein each single-tenant layer comprises a database and business logic of the respective tenant, wherein a multi-tenant encryption scheme is configured to enable secure communications with the multiple tenants without divulging sensitive information to the multi-tenant layer.