An amplifier circuit according to the present invention includes a first block, a second block, a transformer, and a reference node and operates as a negative impedance converter circuit. A circuit configuration formed by a first transistor and at least one first passive component in the first block with respect to a first terminal of the transformer and a circuit configuration formed by a second transistor and at least one second passive component in the second block with respect to a second terminal of the transformer are the same as each other.

An amplifier is configured to amplify an RF signal as between an input terminal and an output terminal across a wideband frequency range. A first LC network is connected to the input terminal and has first and second reactive components. A first switching device is connected between the first and second reactive components and couples both the first and second reactive components to the input terminal in an ON state, and disconnects the second reactive component from the input terminal in an OFF state. A second LC network is connected to the output terminal and has third and fourth reactive components. A second switching device is connected between the third and fourth reactive components and couples both the third and fourth reactive components to the output terminal in an ON state and disconnects the fourth reactive component from the output terminal in in an OFF state.

A dual-mode envelope tracking (ET) power management circuit is provided. An ET amplifier(s) in the dual-mode ET power management circuit is capable of supporting normal-power user equipment (NPUE) mode and high-power user equipment (HPUE) mode. In the NPUE mode, the ET amplifier(s) amplifies a radio frequency (RF) signal(s) to an NPUE voltage based on a supply voltage for transmission in an NPUE output power. In the HPUE mode, the ET amplifier(s) amplifies the RF signal(s) to an HPUE voltage higher than the NPUE voltage based on a boosted supply voltage higher than the supply voltage for transmission in an HPUE output power higher than the NPUE output power. The ET amplifier(s) maintains a constant load line between the NPUE mode and the HPUE mode. By maintaining the constant load line, it is possible to maintain efficiency of the ET amplifier(s) in both the NPUE mode and the HPUE mode.

Reducing a sensitivity of an electromechanical sensor is presented herein. The electromechanical sensor comprises a sensitivity with respect to a variation of a mechanical-to-electrical gain of a sense element of the electromechanical sensor; and a voltage-to-voltage converter component that minimizes the sensitivity by coupling, via a defined feedback capacitance, a positive feedback voltage to a sense electrode of the sense element—the sense element electrically coupled to an input of the voltage-to-voltage converter component. In one example, the voltage-to-voltage converter component minimizes the sensitivity by maintaining, via the defined feedback capacitance, a constant charge at the sense electrode. In another example, the electromechanical sensor comprises a capacitive sense element comprising a first node comprising the sense electrode. Further, a bias voltage component can apply a bias voltage to a second node of the electromechanical sensor. In yet another example, the electromechanical sensor comprises a piezoelectric sense element.

A higher-speed operation of a power amplifier circuit is achieved. A power amplifier circuit includes multi-stage amplifier units, an ET terminal, and an APT terminal. The multi-stage amplifier units include a final-stage amplifier unit. The final-stage amplifier unit includes a first amplifier element and a second amplifier element that are connected in parallel with each other. The first amplifier element is connected to the ET terminal. The second amplifier element is connected to the APT terminal.

A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.

Example embodiments relate to hybrid Doherty power amplifier modules. One embodiment includes a printed circuit board having an input RF terminal and an output RF terminal, and on which printed circuit board a primary Doherty amplifier is integrated. The primary Doherty amplifier includes a primary Doherty splitter arranged on the printed circuit board and configured for splitting an input RF signal received at the input RF terminal into a plurality of RF signal components. The primary Doherty amplifier also includes a plurality of amplifying paths, each amplifying path being partially integrated on a semiconductor die of a first kind mounted on the printed circuit board and partially integrated on a semiconductor die of a second kind mounted on the printed circuit board. Further, the primary Doherty amplifier includes a primary Doherty combiner arranged on the printed circuit board.

A Class D amplifier comprising a control circuit configured to receive an audio input signal and derive first, second and third PWM switching control signals therefrom, being supplied to respectively first, second and third switches of a driver, the first and second switches being serially arranged between first and second supply voltages, and having a common node coupled to an output terminal. The driver comprises a DC level shifter being configured to provide a reference voltage to a reference terminal in at least first and second states of operation, said reference voltage including a DC component at least substantially equidistant between the first and second supply voltages. Said third switch being included in a shunt path between the output and the reference terminal.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An electronic device for detecting the weight of a capsule for a pharmaceutical product is provided with: a plurality of detection electrodes, which face a respective one of a plurality of sectors into which the capsule is divided in a main extension direction thereof, each one of the detection electrodes forming a respective detection capacitor with a common plate defined by a capsule-holding element which holds the capsule; and an electronic circuit having a plurality of detection stages, each operatively coupled to a respective one of the detection electrodes so as to detect, in an independent and exclusive manner, a capacitive variation of the respective detection capacitor and to generate a respective output quantity, which is a function of the capacitive variation and indicative of the weight of the respective sector of the capsule.