Systems, apparatuses, and methods for efficient operation of a switch arrangement are described. Selectively operating one of a plurality of parallel-connected switches at different times along a period of a periodic waveform may allow for improved efficiency, uniform loss-spreading, and enhanced thermal design of an electronic circuit including use of power switches.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

A method for controlling a first and a second reverse-conducting insulated gate bipolar transistor (RC-IGBT), electrically connected in series, is disclosed. A collector of the first RC-IGBT is electrically connected to a positive pole of a direct current voltage source, and an emitter of the second RC-IGBT is electrically connected to a negative pole of the DC voltage source. Further, an emitter of the first RC-IGBT is electrically connected to a collector of the second RC-IGBT to form an alternating current terminal. A gate voltage is applied to respective gates of the first and second RC-IGBTs, wherein the gate voltage is controlled based on a magnitude and a direction of an output current on the AC terminal and on a command signal alternating between a first and a second value.

Disclosed is a high voltage power system with enable control, comprising a high voltage start-up circuit, a PWM control module, and a driving module; the high voltage start-up circuit comprises a first transistor, a third transistor, a fourth transistor, a resistor, a diode, a VDD detection unit and an I/O interface unit; the high voltage start-up circuit is controlled by an input of a pin EN; when the pin EN is set, the high voltage start-up circuit stops working; the power system is shut off and doesn't restart, and enters a zero standby state; when the pin EN is reset, the high voltage start-up circuit restores to work, and the power system restarts and enters a normal working state. The power system having the high voltage start-up circuit with enable control has characteristics that the standby input power consumption and standby input current are both close to zero.

A bootstrapping circuit that utilizes multiple pre-charged capacitor voltages and applies the capacitor voltages to the high side FET of a GaN bootstrapping driver. During the pre-charging phase of the bootstrapping driver, multiple capacitors are charged in parallel to the supply voltage. During the driving phase of the bootstrapping driver, the capacitors are connected in series through a number of FETs and connected to the gate terminal of the high side FET of the bootstrapping driver. As a result, the gate-to-source voltage of the high side FET is equal to or greater than the supply voltage during the driving phase, increasing the driving capability of the high side FET and reducing the total required capacitance and die area of the bootstrapping driver.

Provided is a drive circuit 1 including: a switching unit 3 including a first transistor Tr1 that constitutes an upper arm, and a second transistor Tr2 that is connected to the first transistor Tr1 in series and constitutes a lower arm; and a drive power supply 5 in which a positive electrode is connected to a gate terminal of the first transistor Tr1 and a negative electrode is connected to a source terminal of the second transistor Tr2. When turning off the switching unit 3, the first transistor Tr1 is turned off after the second transistor Tr2 is turned off

A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations.

The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.

A system includes a switching converter with an output inductor. The switching converter also includes a switch set with a switch node coupled to the output inductor. The switching converter also includes a first drive stage coupled to the switch set. The switching converter also includes a second drive stage coupled to the switch set. The switching converter also includes a controller coupled to the first drive stage and the second drive stage. The controller includes a supply voltage detector circuit. The controller also includes a level shifter coupled to an output of the supply voltage detector circuit. The controller also includes a selection circuit coupled between the level shifter and the second drive stage.

A power conversion apparatus includes a semiconductor module including a semiconductor device and a control circuit unit controlling the semiconductor module. The semiconductor module has main and subsidiary semiconductor devices connected in parallel. The control circuit unit performs control such that the subsidiary semiconductor device is turned on after the main semiconductor device is turned on, and the main semiconductor device is turned off after the subsidiary semiconductor device is turned off. The control circuit unit performs control such that, one of the turn-on and turn-off switching timings has a switching speed faster than that of the other of the switching timings. The semiconductor module is configured such that, at a high-speed switching timing, an induction current directed to turn off the subsidiary semiconductor device is generated in a control terminal of the subsidiary semiconductor device depending on temporal change of a main current flowing to the main semiconductor device.

A gate driving circuit of embodiments is provided with a first transistor which controls a gate-on voltage applied to a gate electrode of a switching device, a second transistor which controls a gate-off voltage applied to the gate electrode of the switching device, a driving logic circuit which controls turn-on/turn-off of the first and second transistors, a first power source which supplies the gate-on voltage to the gate electrode when the first transistor is turned on, a second power source which supplies the gate-off voltage to the gate electrode when the second transistor is turned on, a first gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, a second gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, and a gate resistance control circuit which controls gate voltages of a plurality of field effect transistors.