H10N52/101

METHOD FOR MANUFACTURING A HALL SENSOR
20170358736 · 2017-12-14 · ·

A method for manufacturing a Hall sensor, an insulation layer being initially applied to a wafer including an ASIC or integrated into the wafer, a Hall layer, for example, made of InSb or another III-V semiconductor material, being situated thereon, and this Hall layer being at least sectionally recrystallized with the aid of a laser. The insulation layer may be porous or may include a cavity or reflective layer for thermal protection of the ASIC.

ASSEMBLING OF MOLECULES ON A 2D MATERIAL AND AN ELECTRONIC DEVICE
20230187544 · 2023-06-15 · ·

The present invention relates to a method for assembling molecules on the surface of a two-dimensional material formed on a substrate, the method comprises: forming a spacer layer comprising at least one of an electrically insulating compound or a semiconductor compound on the surface of the two-dimensional material, depositing molecules on the spacer layer, annealing the substrate with spacer layer and the molecules at an elevated temperature for an annealing time duration, wherein the temperature and annealing time are such that at least a portion of the molecules are allowed to diffuse through the spacer layer towards the surface of the two-dimensional material to assemble on the surface of the two-dimensional material. The invention also relates to an electronic device.

HALL SENSOR DEVICE AND HALL SENSING METHOD
20170345997 · 2017-11-30 ·

The present disclosure relates to 3-dimensional Hall sensor devices comprising a Hall sensor element having a Hall effect region implemented in a 3-dimensional shell and comprising at least three terminals. Each terminal is connected to at least one electrical contact of the Hall effect region and each electrical contact is disposed at a different region of the 3-dimensional shell. The present disclosure further discloses spinning current/voltage schemes for offset cancellation in such 3-dimensional Hall sensor devices.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

A method for manufacturing semiconductor devices is provided. The method includes bonding a semiconductor element to a first surface of a planar lead frame, clamping a partial area of the lead frame to hold the lead frame and the semiconductor element in molding dies, and covering at least a part of the lead frame and the semiconductor element with a resin member by resin molding which fills the molding dies with resin. A thin-walled portion having a relative small thickness is previously formed on a shortest virtual line connecting a clamp area of the lead frame to an area where the semiconductor element is bonded.

Hall device
11678588 · 2023-06-13 · ·

A Hall effect device includes a semiconductor region and at least three contacts to the semiconductor region, which are arranged in the semiconductor region substantially along a line or curve. The line or curve functionally separates the semiconductor region in a first region and a second region. The Hall effect device further including a first electrode that is electrically isolated against the first region and a second electrode that is electrically isolated against the second region. Two of the at least three contacts supply electric energy to the first region and to the second region, and the remaining at least one contact taps an output signal of the first region and/or the second region that responds to a magnetic field component.

SENSOR MODULE AND METHOD OF MANUFACTURE
20170328964 · 2017-11-16 ·

According to embodiments there is provided a magneto-resistive sensor module. The sensor module may comprise: an integrated circuit; magneto-resistive sensor elements arranged as a bridge circuit monolithically integrated on the integrated circuit; and a stress buffer layer arranged between the integrated circuit and the magneto-resistive sensor element. There is also a provided a method of manufacturing the magneto-resistive sensor module.

Power semiconductor module having a current sensor module fixed with potting material

Described is a power semiconductor module that includes: a frame made of an electrically insulative material; a first substrate seated in the frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a busbar extending from the first substrate through a side face of the frame; a current sensor module seated in a receptacle of the frame in sensing proximity of the busbar, the current sensor module including a current sensor attached to a circuit board; and a potting material fixing the current sensor module to the frame such that no air gap is present between the current sensor and the busbar. The potting material contacts the frame and the current sensor. Methods of producing the power semiconductor module are also described.

NORMALLY-OFF MODE POLARIZATION SUPER JUNCTION GaN-BASED FIELD EFFECT TRANSISTOR AND ELECTRICAL EQUIPMENT
20230170407 · 2023-06-01 ·

This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type In.sub.yGa.sub.1-yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12 and a p-type In.sub.zGa.sub.1-zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the Al.sub.xGa.sub.1-xN layer 12. The gate electrode 20 may be provided on the p-type In.sub.zGa.sub.1-zN layer 19 via a gate insulating film. At a non-operating time, n.sub.0≤n.sub.1<n.sub.2<n.sub.3 is satisfied for the concentration n.sub.0 of the 2DEG 22 formed in the undoped GaN layer 11/the Al.sub.xGa.sub.1-xN layer 12 hetero-interface just below the gate electrode 20, the concentration n.sub.1 of the 2DEG 22 just below the gate electrode 16, the concentration n.sub.2 of the 2DEG 22 in the polarization super junction region and the concentration n.sub.3 of the 2DEG 22 in the part between the polarization super junction region and the drain electrode 18.

Semiconductor device with embedded magnetic flux concentrator

A magnetic flux concentrator (MFC) structure comprises a substrate, a first metal layer disposed on or over the substrate, and a second metal layer disposed on or over the first metal layer. Each metal layer comprises (i) a first wire layer comprising first wires conducting electrical signals, and (ii) a first dielectric layer disposed on the first wire layer. A magnetic flux concentrator is disposed at least partially in the first metal layer, in the second metal layer, or in both the first and the second metal layers. The structure can comprise an electronic circuit or a magnetic sensor with sensing plates. The structure can comprise a transformer or an electromagnet with suitable control circuits. The magnetic flux concentrator can comprise a metal stress-reduction layer in the first or second wire layers and a core formed by electroplating the stress-reduction layer.

SPIN TRANSPORT ELECTRONIC DEVICE

An electronic device is presented, the device comprises: a spin accumulating structure; a spin selective filter electrically connected at a first end thereof to a first surface of said spin accumulating layer structure; a charge carrier source attached to said spin selective filter at a second end of the spin selective filter; wherein the spin selective filter is configured to allow passage of the charge carriers having a predetermined spin orientation from the charge carrier source to the spin accumulating structure, thereby causing a variation of spin distribution of the charge carriers within the spin accumulating structure. The device comprises further at least first and second pairs of electrical contacts which are connected to the spin accumulating structure and define first and second electrical paths through said spin accumulating structure, said first and second electrical paths intersecting within said spin accumulating structure. The device including a circuit configured to apply an electrical current between the first pair of electrical contacts and to detect the variation of spin-distribution of charge carriers within the spin accumulating structure by determining electrical voltage between the second pair of electrical contacts in response to the applied electrical current.