An LC resonance element (10) includes a dielectric film (12), a common electrode (11) formed of a thin-film conductor on a lower surface (12D) of the dielectric film, a first capacitor (C1) and a second capacitor (C2) that are connected in series via the common electrode (11) and constitute a thin-film capacitor (TC), first and second external connection terminals (14A, 14B) formed on an upper surface (12U) of the dielectric film, a thin-film conductive wire (16) constituting a thin-film inductor (TL), a first upper electrode (13A) of the first capacitor formed on the upper surface (12U), and a second upper electrode (13B) of the second capacitor formed on the upper surface (12U). The thin-film conductive wire (16) is formed in a region (R2) located on the upper surface (12U) of the dielectric film and outside the common electrode (11) in plan view.

A dielectric film layer structure and a fabricating method thereof are provided. The dielectric film layer structure at least has a first capacitor electrode, a dielectric layer, and a second capacitor electrode, wherein the dielectric layer includes two materials of SiNx and SiOx. In a place where voltage drop is relatively large, the dielectric layer is mainly made of SiNx, and in a place where the voltage drop is relatively small, the dielectric layer is mainly made of SiOx, thereby changing current for charging thin film transistors, reducing influence of the voltage drop, and improving uniformity of panel voltage output.

A thin film capacitor includes a capacitance portion in which a plurality of electrode layers and dielectric layers are alternately laminated, a cover layer, an insulating layer, a via hole in which one electrode layer different from an uppermost electrode layer among the plurality of electrode layers is exposed at a bottom surface thereof, and an opening which is provided inside the via hole and in which the one electrode layer is exposed at a bottom surface thereof, and in which the cover layer and the insulating layer are exposed at a side surface. The opening includes a first opening portion which passes through the insulating layer and a second opening portion which is provided below the first opening portion and passes through the cover layer, and when an inner diameter of the first opening portion is D1 and an inner diameter of the second opening portion is D2, D1>D2.

Disclosed herein a thin film capacitor that includes a lower electrode layer, an upper electrode layer, and a dielectric layer disposed between the lower electrode layer and the upper electrode layer. The dielectric layer has a through hole. The upper electrode layer has a connection part connected to the lower electrode layer through the through hole and an electrode part insulated from the connection part by a slit. A surface of the lower electrode layer that contacts the connection part through the through hole includes an annular area positioned along an inner wall surface of the through hole and a center area surrounded by the annular area. The annular area is lower in surface roughness than the center area.

Disclosed herein a thin film capacitor that includes a lower electrode layer, an upper electrode layer, and a dielectric layer disposed between the lower electrode layer and the upper electrode layer. The dielectric layer has a through hole. An inner wall surface of the through hole has a first tapered surface and a second tapered surface surrounded by the first tapered surface. The first and second tapered surfaces are not covered with the upper electrode layer and have respective first and second taper angles with respect to a surface of the lower electrode layer. The second taper angle is smaller than the first taper angle.

An electronic device comprises a first blocking electrode; a second blocking electrode; and a dielectric material disposed between the first electrode and the second electrode, the dielectric material comprising a compound of Formula 1
Li.sub.24-b*y-c*z-a*xM.sup.1.sub.yM.sup.2.sub.zM.sup.3.sub.xO.sub.12-δ  (1)
wherein M.sup.1 is a cationic element having an oxidation state of b, wherein b is +1, +2, +3, +4, +5, +6, or a combination thereof; M.sup.2 is a cationic element having an oxidation state of c, wherein c is +1, +2, +3, +4, +5, +6, or a combination thereof; M.sup.3 is a cationic element having an oxidation state of a, wherein a is +1, +3, +4, or a combination thereof; 0≤y≤3; 0≤z≤3; 0≤x≤5; and 0≤δ≤2. Methods for the manufacture of the electronic device are also disclosed.

A capacitor is provided that includes a base having a first main surface and a second main surface opposing each other with a trench formed on a side of the first main surface (110A. Moreover, a dielectric film is disposed in a region that includes an inside of the trench on the side of the first main surface of the base; a conductor film is provided that includes a first conductor layer disposed on the dielectric film, which is the region including the inside of the trench and a second conductor layer disposed on the first conductor layer; and a stress relieving portion is provided in contact with at least a part of the end of the first conductor layer. Moreover, a thickness of the stress relieving portion is smaller than a thickness of the conductor film, outside the trench portion of the first main surface of the base.

A method for manufacturing a multilayer electronic component having an element body in which a functional part and a conductor part are laminated. The green multilayer body 11 is formed on the temporary holding film 62 formed on the release substrate. The green multilayer body 11 is formed by repeating the first step forming a green functional part using the first ink containing the functional particles and the second step forming the green conductor part using the second ink containing the conductive particles. The temporary holding film 62 has conductivity.

A ceramic electronic device includes a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, wherein a main component of the dielectric layers is (Ba, Sr, Ca)(Zr, Ti)O.sub.3, wherein a Ba concentration and a Ca concentration have variation in at least one of crystal grains in the dielectric layers.

MIM capacitors using low temperature sub-nanometer periodic stack dielectrics (SN-PSD) containing repeating units of alternating high dielectric constant materials sublayer and low leakage dielectric sublayer are provided. Every sublayer has thickness less than 1 nm (sub nanometer). The high dielectric constant materials could be one or more different materials. The low leakage dielectric materials could be one or more different materials. For the SN-PSD containing more than two different materials, those materials are deposited in sequence with the leakage current of the materials from the lowest to the highest and then back to the second-lowest, or with the energy band gap of the materials from the widest to the narrowest and then back to the second widest in each periodic cell. A layer of low leakage current dielectric materials is deposited on and/or under SN-PSD. The dielectric constant of SN-PSD is much larger than that of the component oxides and can be readily deposited at 250 C. using atomic layer deposition (ALD). The ALD deposition cycle could be 20-1000 cycles. The deposition technology is not limited to ALD, could be thermal oxidation, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and other thermal source assisted deposition.