A wire guide module for an ultrasonic wire bonder, comprising a body made of a thermally stable metallic and/or ceramic material, wherein an elongated wire feed-through channel having a wire inlet opening and having a wire outlet opening is provided on the body, and comprising a guide tube provided in the wire feed-through channel. In addition, the invention relates to a thermosonic wire bonder having a wire guide module.

Method and arrangement for assembling one or more microchips (415; 615; 715; 815; 915; 1015) into one or more holes (422; 722), respectively, in a substrate surface (421; 721) of a separate receiving substrate (420; 720; 820; 1020). The holes (422; 722) of the substrate is for microchip insertion out-of-plane in relation to said substrate surface. Each of said microchips is provided with a ferromagnetic layer (213; 613) of ferromagnetic material. The microchips are placed (503) on said substrate surface (421; 721) and it is applied and moved (504) one or more magnetic fields affecting said ferromagnetic layer (213; 613) of each microchip such that the microchips thereby become out-of-plane oriented in relation to said substrate surface (421; 721) and move over the substrate surface (421; 721) until assembled into said holes (422; 722).

A semiconductor package including: a package substrate; a spacer chip attached on a surface of the package substrate, the spacer chip having a groove pattern in a surface of the spacer chip; at least one semiconductor chip mounted on the package substrate, the at least one semiconductor chip being attached on the surface of the spacer chip via an adhesive film; and a sealing member on the surface of the package substrate, the sealing member covering the spacer chip and the at least one semiconductor chip.

There is provided a semiconductor module capable of preventing the adhesion of an epoxy resin to terminals to which at least one of a large current and a high voltage is supplied. A semiconductor module includes: a sealing section formed of an epoxy resin and sealing transistors; an intermediate terminal having a fastening surface to which a cable connected to a load as a drive target is fastened in a direction intersecting the thickness direction of a sealing section and connected to the transistors; and a structure arranged between the sealing section and the fastening surface and having an input section higher than a surface of the sealing section and the fastening surface.

An ultrasound horn is provided which vibrates a bonding tool, attached at a tip, in a plurality of directions with a simple structure. There is provided an ultrasound horn having: a longitudinal vibration generator; a horn portion; and a torsional vibration generator. The torsional vibration generator includes a body including a polygonal pillar portion, second layered elements in which a plurality of second piezoelectric elements are layered, and which are attached to side surfaces of the polygonal pillar portion, weights, and a pressure application ring which applies a pressure by pressing the second piezoelectric elements against the polygonal pillar portion via the weights.

A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

A semiconductor package includes a package substrate, a semiconductor chip and a plurality of bonding wires. The package substrate includes a connection pad. The semiconductor chip is disposed over the package substrate and includes a chip pad, a bonding pad, and a redistribution layer. The bonding pad is closer to a periphery of the semiconductor chip than the chip pad. The redistribution layer is connected between the chip pad and the bonding pad. The bonding wires are connected in parallel between the connection pad and the bonding pad.

A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

A display substrate, including: a base substrate including at least a side edge and a display area; a plurality of pixel units disposed in the display area, a second pixel unit is located on a side of a first pixel unit close to the side edge, edges of the second pixel unit include the side edge, a third pixel unit is located between the first pixel unit and the second pixel unit, and the third pixel unit is adjacent to the second pixel unit; and a plurality of light emitting diode chips disposed on the base substrate a first light emitting diode chip is located in the first pixel unit, a part of a second light emitting diode chip is located in the second pixel unit, and the other part of the second light emitting diode chip is located in the third pixel unit.