A method of manufacturing a packaged semiconductor device is provided. The method includes placing a plurality of semiconductor die on a carrier substrate. The plurality of semiconductor die and an exposed portion of the carrier substrate are encapsulated with an encapsulant. A cooling fixture includes a plurality of nozzles and is placed over the encapsulant. The encapsulant is cooled by way of air exiting the plurality of nozzles. A property of air exiting a first nozzle of the plurality of nozzles is different from that of a second nozzle of the plurality of nozzles.

A semiconductor die is disclosed. The semiconductor die includes a semiconductor body, a metallization over part of the semiconductor body and including a noble metal at a top surface of the metallization, a bondwire having a foot bonded to the top surface of the metallization, and a sealing material covering the foot of the bondwire, the top surface of the metallization, and one or more areas outside the top surface of the metallization where oxide and/or hydroxide-groups would be present if exposed to air. The sealing material adheres to the foot of the bondwire and the one or more areas outside the top surface of the metallization where the oxide and/or hydroxide-groups would be present if exposed to air.

A protective film substance for laser processing includes a solution including a water-soluble resin, an organic solvent, and a light absorbent. The solution has an absorbance, i.e., an absorbance converted for a solution diluted 200 times, equal to 0.05 or more per an optical path length of 1 cm at a wavelength of 532 nm. Alternatively, the protective film substance for laser processing includes a solution including a water-soluble resin, an organic solvent, and a polyhydroxyanthraquinone derivative.

In one embodiment, a semiconductor device includes a first substrate with a transistor formed in a first active are, a first bonding pad electrically connected to the transistor and a first metal pad surrounding the first active area. A second substrate of a type that is different from the first substrate includes a passive circuit element in a second active area on a front surface, a second bonding pad electrically connected to the passive circuit element, a second metal pad surrounding the second active area, and a mounting pad on a back surface of the second substrate with a through-via electrically connecting the second bonding pad to the mounting pad. A first interconnection extends from the first bonding pad to the second bonding pad, and a second interconnection extends from the first metal pad to the second metal pad and surrounds the region through which the first interconnection extends.

A semiconductor device has a substrate. A semiconductor die including a photosensitive circuit is disposed over the substrate. A shield is disposed over the substrate and semiconductor die with a first opening of the shield disposed over the photosensitive circuit. An outer section of the shield is attached to the substrate and includes a second opening. An encapsulant is deposited over the substrate and semiconductor die. The encapsulant extends into the first opening and a first area between the shield and substrate while a second area over the photosensitive circuit remains devoid of the encapsulant.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

A component comprising a structural element, a leadframe and a shaped body, in which component the structural element and the leadframe are enclosed at least in regions by the shaped body in lateral directions and the leadframe does not project beyond side faces of the shaped body. The leadframe has at least one first subregion and at least one second subregion which is laterally spaced apart from the first subregion, wherein the structural element is electrically conductively connected to the second subregion by a planar contact structure. Furthermore, the structural element is arranged, in plan view, on the first subregion and projects laterally beyond the first subregion at least in regions, so that the structural element and the first subregion form an anchoring structure at which the structural element and the first subregion are anchored to the shaped body. Further specified is a method for producing such a component.

Disclosed is an apparatus including a molded multi-die high density interconnect including: a bridge die having a first plurality of interconnects and second plurality of interconnects. The apparatus also includes a first die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the first plurality of interconnects of the bridge die. The apparatus also includes a second die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the second plurality of interconnects of the bridge die. The coupled second plurality of contacts and interconnects have a smaller height than the first plurality of contacts of the first die and second die.

A semiconductor package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. The redistribution structure overlays the encapsulated semiconductor device and includes a plurality of vias and a redistribution line. The plurality of vias are located on different layers of the redistribution structure respectively and connected to one another through a plurality of conductive lines, wherein, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines. The redistribution line is disposed under the plurality of conductive lines and connects corresponding one of the plurality of vias and electrically connected to the semiconductor device through the plurality of vias.

A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least one portion of the encapsulant is spaced from the carrier by a space.