A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

The present disclosure relates to a Schottky diode having a drift layer and a Schottky layer. The drift layer is predominantly doped with a doping material of a first conductivity type and has a first surface associated with an active region. The Schottky layer is provided over the active region of the first surface to form a Schottky junction. A plurality of junction barrier elements are formed in the drift layer below the Schottky junction, and a plurality of central implants are also formed in the drift layer below the Schottky junction. In certain embodiments, at least one central implant is provided between each adjacent pair of junction barrier elements.

One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

A semiconductor device includes: a semiconductor region having charge carriers of a first conductivity type; a transistor cell in the semiconductor region; a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region in the semiconductor region and having a second doping concentration of charge carriers of the second conductivity type. A transition between the semiconductor auxiliary region and semiconductor region forms a second pn-junction positioned deeper in the semiconductor region as compared to the first pn-junction. The semiconductor auxiliary region is positioned closest to the semiconductor channel region as compared to any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

A super-junction semiconductor device with an enlarged process window for a desirable breakdown voltage includes: a semiconductor substrate and an epitaxial layer deposited on the semiconductor substrate. The epitaxial layer includes a first semiconductor layer, and a second semiconductor layer disposed on the first semiconductor layer. A band gap of the first semiconductor layer is greater than a band gap of the second semiconductor layer. A super-junction structure is formed in the epitaxial layer, including at least one first epitaxial pillar of a first dopant type, and at least one second epitaxial pillar of a second dopant type. The first epitaxial pillar and the second epitaxial pillar are alternately arranged along a transverse direction. The epitaxial layer has a sandwich structure.

A high-speed diode includes an n-type semiconductor layer and a p-type semiconductor layer which is laminated on the n-type semiconductor layer, where a pn junction is formed in a boundary portion between the n-type semiconductor layer and the p-type semiconductor layer, and crystal defects are formed such that the frequency of appearance is gradually decreased from the upper surface of the p-type semiconductor layer toward the bottom surface of the n-type semiconductor layer.

A three-dimensional semiconductor wafer relates to a semiconductor wafer, including a raw semiconductor wafer, at least one connection layer, a conduction layer and a protection layer, wherein the protection layer is arranged on the conduction layer; the connection layer is inserted into a bottom surface or/and a top surface of the raw semiconductor wafer; and the conduction layer is arranged on the bottom surface of the raw semiconductor wafer.

This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type In.sub.yGa.sub.1-yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12 and a p-type In.sub.zGa.sub.1-zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the Al.sub.xGa.sub.1-xN layer 12. The gate electrode 20 may be provided on the p-type In.sub.zGa.sub.1-zN layer 19 via a gate insulating film. At a non-operating time, n.sub.0≤n.sub.1<n.sub.2<n.sub.3 is satisfied for the concentration n.sub.0 of the 2DEG 22 formed in the undoped GaN layer 11/the Al.sub.xGa.sub.1-xN layer 12 hetero-interface just below the gate electrode 20, the concentration n.sub.1 of the 2DEG 22 just below the gate electrode 16, the concentration n.sub.2 of the 2DEG 22 in the polarization super junction region and the concentration n.sub.3 of the 2DEG 22 in the part between the polarization super junction region and the drain electrode 18.

A resistor element encompasses a first resistive layer, a first protection strip implemented by a tandem connection of p-n junctions, an interlayer insulating film covering the first resistive layer and the first protection strip, a first external electrode on the interlayer insulating film, being connected to a terminal of the first resistive layer and a terminal of the first protection strip, and a second external electrode on the interlayer insulating film, being connected to another terminal of the first resistive layer and another terminal of the first protection strip.

A semiconductor device has transistor portions and diode portions. The transistor portions have a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type, second semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, a first semiconductor layer of the first conductivity type, a third semiconductor region of the second conductivity type, a first electrode, and a second electrode. The diode portions have the semiconductor substrate, the first semiconductor region, the first semiconductor layer, a fourth semiconductor region of the first conductivity type, the first electrode, and the second electrode. The first semiconductor layer has a predetermined region, a depth of the predetermined region from a second main surface of the semiconductor substrate is greater than a depth of a region of the first semiconductor layer excluding the predetermined region, from the second main surface of the semiconductor substrate.