Patent classifications
H01L2224/04
INTEGRATED CIRCUIT ASSEMBLY
An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.
Optical coupling module
An optical coupling module includes a silicon photonic substrate, and an optical waveguide module. The silicon photonic substrate has a first surface and a first grating on the first surface for diffracting the light which passes through the grating. The optical waveguide module is disposed on the silicon photonic substrate, wherein the optical waveguide module includes an optical waveguide having an end disposed in corresponding to the first grating of the silicon photonic substrate. Otherwise, the optical waveguide module has a reflective surface coupled to the end of the optical waveguide and adapted to reflect the light emerging from or incident into the grating to form an optical path between the silicon photonic substrate and the optical waveguide for transmitting the light.
Optical coupling module
An optical coupling module includes a silicon photonic substrate, and an optical waveguide module. The silicon photonic substrate has a first surface and a first grating on the first surface for diffracting the light which passes through the grating. The optical waveguide module is disposed on the silicon photonic substrate, wherein the optical waveguide module includes an optical waveguide having an end disposed in corresponding to the first grating of the silicon photonic substrate. Otherwise, the optical waveguide module has a reflective surface coupled to the end of the optical waveguide and adapted to reflect the light emerging from or incident into the grating to form an optical path between the silicon photonic substrate and the optical waveguide for transmitting the light.
Electrode connection structure and electrode connection method
An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.
Electrode connection structure and electrode connection method
An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a display device includes: immersing a mask including openings, in a solution; seating light-emitting diode chips respectively in the openings of the mask; arranging a first flexible substrate including first wirings thereon, below the mask, and aligning the first wirings to respectively correspond to the openings of the mask; removing from the solution, the first flexible substrate with the first wirings corresponding to the openings of the mask together with the mask with the light-emitting diode chips seated in the openings thereof; bonding the light-emitting diode chips and the first wirings to each other; providing a second flexible substrate including second wirings thereon, and aligning the second wirings to respectively correspond to the light-emitting diode chips; and bonding the light-emitting diode chips and the second wirings to each other, to form the display device.
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a display device includes: immersing a mask including openings, in a solution; seating light-emitting diode chips respectively in the openings of the mask; arranging a first flexible substrate including first wirings thereon, below the mask, and aligning the first wirings to respectively correspond to the openings of the mask; removing from the solution, the first flexible substrate with the first wirings corresponding to the openings of the mask together with the mask with the light-emitting diode chips seated in the openings thereof; bonding the light-emitting diode chips and the first wirings to each other; providing a second flexible substrate including second wirings thereon, and aligning the second wirings to respectively correspond to the light-emitting diode chips; and bonding the light-emitting diode chips and the second wirings to each other, to form the display device.
Chip package structure
A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.
Circuit substrate interconnect
A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.
Circuit substrate interconnect
A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.