In order to easily inspect a dispersion state of conductive particles in such an anisotropic conductive film that the conductive particles are dispersed even at high density, linear lines including no conductive particle in a plan view of an anisotropic conductive film including an insulating adhesive layer and conductive particles dispersed in the insulating adhesive layer are allowed to exist at predetermined intervals. Specifically, the conductive particles are disposed in a lattice so as to be arranged in a first arrangement direction and a second arrangement direction, and the disappearance lines are inclined relative to the first arrangement direction or the second arrangement direction.

A wafer bonding system and method using a combination of heat and a pneumatic force to bond two wafers held together in alignment. The wafers are heated via a non-contact, gaseous interface, thermal path between heating elements and the wafers. The pneumatic force is created by a pressure differential between a first pressure surrounding the two wafers and a second pressure, which is less than the first pressure, maintained between the two wafers.

A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.

A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.

A module collection and deposition system comprises a container, a module source wafer comprising modules released from the module source wafer, a module collection device operable to remove the modules from the module source wafer and dispose the modules as a disordered and dry collection into the container, and a module deposition device for removing the modules from the container and randomly disposing the modules on a receiving surface. Each module comprises an electronically active unpackaged component.

This disclosure pertains to hardware compute arrays (sometimes called systolic arrays) for applications such as artificial intelligence (AI), machine learning (ML), digital signal processing (DSP), graphics processing units (GPUs), and other computationally intensive applications. More particularly, it pertains to novel and advantageous architecture innovations for efficiently and inexpensively implementing such arrays using multiple integrated circuits. Hardware and methods are disclosed to allow compute arrays to be tested after face-to-face or wafer-to-wafer bonding and without out any pre-bonding test. Defects discovered in the post-bonding testing can be completely or partially healed increasing yields and reducing costs.

A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate.

A method of manufacturing an electronic device formed in a cavity may include, on a first substrate having a bottom surface and a top surface, forming a first side wall of a certain height along a periphery on the bottom surface to surround an electronic circuit disposed on the bottom surface; forming a via communicating between the bottom surface and the top surface, forming of the via including stacking a first stop layer and a second stop layer sequentially on a portion of the bottom surface of the first substrate corresponding to the via and etching the first substrate to form a through-hole corresponding to the via, a rate of etching the first substrate being greater than that of the first stop layer and a rate of etching the first stop layer being greater than that of the second stop layer; forming a second side wall of a certain height along a periphery on a top surface of the second substrate; and aligning and bonding the first side wall and the second side wall.

Methods of manufacturing an electronic device formed in a cavity may include providing a first substrate having a first side wall including a first metal formed along a periphery on a bottom surface thereof and surrounding an electronic circuit disposed on the bottom surface, providing a second substrate having a second side wall including a second metal and a third metal formed along a periphery on a top surface thereof, aligning the first substrate with the second substrate with the first side wall opposing and contacting the second side wall to internally define a cavity between the bottom surface of the first substrate, the top surface of the second substrate, the first side wall ,and the second side wall, and heating and bonding the first substrate and the second substrate by transient liquid phase bonding.

Methods of preventing water from penetrating inside a pair of bonded wafers that are bonded to one another during manufacture of an electronic device. A method is provided for manufacturing an electronic device including a first substrate having a first side wall of a certain height formed along a periphery to surround an electronic circuit disposed on a bottom surface and a second substrate having a second side wall of a certain height formed along a periphery on a top surface, the second side wall being aligned and bonded with the first side wall. The method includes forming the first side wall on a bottom surface of a first wafer as the bottom surface of the first substrate and forming a first sealing portion of a certain height along a periphery; forming the second side wall on a top surface of a second wafer as the top surface of the second substrate and forming a second sealing portion of a certain height along a periphery; and aligning and bonding the first wafer and the second wafer with each other, the first sealing portion and the first side wall being bonded with the second sealing portion and the second side wall respectively by transient liquid phase bonding.