The present invention relates to an amplifying device and to an amplifying system comprising the same. According to the present invention, an amplifier line-up is presented comprising four amplifying units which is operable in a Doherty mode and an outphasing mode. By integration of Chireix compensating elements in the matching networks used in the amplifying units a bandwidth improvement can be obtained.

A driver circuit for a composite power amplifier configured to operate in at least one Chireix-mode a first and a second sub-amplifier for amplification of an input signal into an output signal is disclosed. An input network of the driver circuit comprises a means configured to provide a first signal which is linearly derivable from the input signal, and a second signal which is non-linearly derivable from the input signal. The input network combines the first signal, at zero degrees phase shift, and the second signal, at 90 degrees phase shift, to obtain a first feeding signal for the first sub-amplifier. Furthermore, the input network combines the first signal, at 180 degrees phase shift, and the second signal, at 90 degrees phase shift, to obtain a second feeding signal for the second sub-amplifier.

An in-line waveguide divider divides power of an incoming high-frequency signal among openings. Amplification boards disposed on a base are provided for respective openings and are each connected in parallel with one another to the in-line waveguide divider. An in-line waveguide combiner includes openings formed correspondingly to the amplification boards, and is connected to the amplification boards. An electrically conductive amplifier cover includes walls formed to provide isolation between circuits of the amplification boards continuously from the in-line waveguide divider to the in-line waveguide combiner, and the entire surface of the amplification boards at the in-line waveguide combiner side is covered with the electrically conductive amplifier cover except openings and openings. Each of the amplification boards includes a waveguide-to-microstrip transition corresponding to the opening, an amplifier element, and a microstrip-to-waveguide transition corresponding to the opening.

A power amplifier circuit includes a first transistor, a capacitor, and a second transistor. The first transistor has an emitter electrically connected to a reference potential, a base, and a collector electrically connected to a first power supply potential. A first end of the capacitor is electrically connected to the collector of the first transistor. The second transistor has an emitter electrically connected to a second end of the capacitor and electrically connected to the reference potential, a base, and a collector electrically connected to the first power supply potential. An RF output signal obtained by amplifying the RF input signal is output from the collector of the second transistor. A second bias circuit includes a third transistor having a collector electrically connected to a second power supply potential, a base, and an emitter from which the second bias current or voltage is output.

A high CMRR neural signal amplifier is configured for supply rail common mode feedback (SR-CMFB) whereby a set of CMFB signals is provided to supply rails of front end LNAs. High CMRR is maintained through buffering outputs of front end signal LNAs and a reference LNA coupled to signal and reference inputs of second stage amplifiers, respectively; and buffering the reference LNA output using an active/guard buffer pair, whereby across a plurality of distinct multiplexing time intervals, during each multiplexing time interval one buffer of the pair functions as an active buffer that drives second stage amplifier reference inputs corresponding to second stage amplifier outputs being multiplexed to a set of multiplexor outputs, and the other buffer of the pair functions as a guard buffer coupled to other second stage amplifier reference inputs corresponding to second stage amplifier outputs not being multiplexed to the set of multiplexor outputs.

Described are circuits and techniques to increase the efficiency of radio-frequency (rf) amplifiers including rf power amplifiers (PAs) through “supply modulation” (also referred to as “drain modulation” or “collector modulation”), in which supply voltages provided to rf amplifiers is adjusted dynamically (“modulated”) overtime depending upon the rf signal being synthesized. For the largest efficiency improvements, a supply voltage can be adjusted among discrete voltage levels or continuously on a short time scale. The supply voltages (or voltage levels) provided to an rf amplifier may also be adapted to accommodate longer-term changes in desired rf envelope such as associated with adapting transmitter output strength to minimize errors in data transfer, for rf “traffic” variations.

An amplifier includes a first circuitry, a second circuitry, and a plurality of amplifier circuitries. The first circuitry controls an enable signal. The second circuitry controls a bias signal. Circuitries which output signals are decided from among the plurality of circuitries based on the enable signal, and each of the circuitries which output the signals amplifies an input signal with a gain corresponding to the bias signal.

Circuitry, which includes a package interface, a radio frequency (RF) amplification circuit, and a closed-loop gain linearization circuit. The package interface receives an RF signal and provides an amplified RF signal. The RF amplification circuit amplifies the RF signal in accordance with a gain of the RF amplification circuit so as to generate the amplified RF signal. In one embodiment, the closed-loop gain linearization circuit is configured to endogenously establish a target gain magnitude using the RF signal and linearize the gain of the RF amplification circuit in accordance with the target gain magnitude. By endogenously establishing the target gain magnitude using the RF signal, the closed-loop gain linearization circuit can provide linearity with greater independence from external control circuitry.

A multistage linear power amplifier receiving an input signal. The multistage linear power amplifier comprises a plurality of Class-AB amplifiers connected in a cascade configuration. The plurality of Class-AB amplifiers amplifies the input signal to generate an amplified input signal. At least one of the plurality of Class-AB amplifiers is biased such that the multistage linear power amplifier emulates a Class-C amplifier.

A solid-state amplifier architecture is disclosed. In some embodiments, the disclosed architecture may include first and second channel chipsets configured to amplify either the entire instantaneous frequency band of a radio frequency (RF) input signal or, respectively, sub-bands thereof, which may be divided proportionally between the two chipsets. In some cases, the chipsets may be configured to amplify frequencies in excess of the entire K-band and K.sub.a-band frequencies simultaneously. In some cases, the architecture may be configured to address a signal received, for instance, from an electronic warfare (EW) system to a log amplifier stage configured to output a signal to the EW system, in response to which the EW system may generate a RF signal for amplification by the architecture for transmission. To facilitate heat dissipation, the architecture may be coupled, in part or in whole, with a thermally conductive carrier, optionally with an intervening diamond heat spreader layer.