Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

A multichannel transmission system which includes a calibration functionality that allows precise calibration of the frequency conversion chains and of the multiport amplifier of the system to be performed without interruption of service. The proposed calibration makes it possible to correct the defects over the entire frequency band of the system.

A modulated signal generating device for modulating includes a first amplifier that generates a first amplified signal based on a first control signal; a second amplifier that has a smaller amplification factor as compared to the first amplifier and that generates a second amplified signal based on a second control signal; a combiner that combines the first amplified signal and the second amplified signal and generates a modulated signal; a first control unit that generates the first control signal based on a first component signal included in a input signal; a first filter that eliminates the harmonic component included in a first difference signal, which represents the difference between the input signal and the first component signal, and generates a first filtered signal; and a second control unit that generates the second control signal based on a second component signal included in the first filtered signal.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

A multi-voltage generation circuit and related envelope tracking (ET) amplifier apparatus is provided. In one aspect, a multi-voltage generation circuit is configured to generate a number of ET target voltages based on an analog voltage signal. In another aspect, a multi-amplifier ET circuit can be configured to include a number of amplifier circuits for amplifying concurrently a radio frequency (RF) signal based on a number of ET voltages. The multi-amplifier ET circuit also includes a number of driver circuits configured to generate the ET voltages base on a number of ET target voltages. In this regard, the multi-voltage generation circuit can be provided in the multi-amplifier ET circuit to generate the ET target voltages based on the analog voltage signal that corresponds to the RF signal. In examples discussed herein, the driver circuits are co-located with the amplifier circuits to help improve efficiency and maintain linearity in the amplifier circuits.

A radio-frequency circuit includes a power amplifying circuit configured to amplify a first radio-frequency signal having a first channel bandwidth and a second radio-frequency signal having a second channel bandwidth greater than the first channel bandwidth. The power amplifying circuit is configured to amplify the first radio-frequency signal in an amplifying mode according to an envelope tracking method, and to amplify the second radio-frequency signal in an amplifying mode according to an average power tracking method.

Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

A payload subsystem of a satellite includes a plurality of transmit antenna feeds, a plurality of frequency filters, and a power amplification arrangement including a plurality of power amplifiers. The power amplification arrangement has at least one multiport amplifier, the multiport amplifier including a plurality of output ports, each output port coupled with a respective one of the plurality of transmit antenna feeds by way of a respective one of the plurality of frequency filters.

A power amplifier, a power amplifier system, and an operating method thereof are provided. The power amplifier system may include a power amplifier, a power amplifier controller, and a voltage generator. The power amplifier may include a plurality of power transistor cells each of which receives an RF signal through a control terminal thereof to amplify the RF signal. The power amplifier controller may control turn-on and turn-off operations of at least one power transistor cell among the plurality of power transistor cells based on a power mode. The voltage generator may generate a power supply voltage supplied to first terminals of the power transistor cells and may change the power supply voltage depending on the power mode.

A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.