The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.

A successive approximation (SA) AD converter includes a SA control circuit generating a digital output signal based on an output from a comparator; a first capacitor coupled to an input of the comparator, receiving an analog input signal, and capable of storing electric charges; a second and a third capacitor groups coupling to a reference voltage and storing electric charges previously. The SA control circuit operates for each SA step that the second or the third capacitor group is coupled to a non-inverting input of the comparator and the other is coupled to an inverting input of the comparator based on the output from the comparator. The SA control circuit operates that capacitor terminals of the second and the third capacitor groups coupled to the input of the comparator have the same potential when the reference voltage is stored previously in the second and the third capacitor groups.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain. In the present disclosure, a capacitor voltage coefficient can be extracted based on INL and the capacitor voltage coefficient is calibrated at a digital backend without adding an analog calibration circuit, thereby improving conversion accuracy of the ADC.

Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.

A broadband digitizer for an applied broadband analog input signal SA(t). The digitizer includes a low frequency analog-to-digital converter (LF ADC) channel and a high frequency analog-to-digital converter (HF ADC) channel, an input splitter coupled to respective inputs to the LF ADC channel HF ADC channels, a frequency divider, and a combining unit. Low frequency portions of SA(t) are digitized to digital signal SD.sub.LF[n] in the LF ADC channel and high frequency portions of SA(t) are digitized to digital signal SD.sub.HF[n] in the HF ADC channel. The combining unit combines the digital signals SD.sub.LF[n] and SD.sub.HF[n] to form distortion-reduced SD[n], corresponding to SA(t). Front ends of the LF ADC channel and HF ADC channel reduce level-caused distortions, and the combining unit reduces ADC frequency-caused, time-position-caused, and interpolation-caused distortions.

Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.

The present invention is a computationally-efficient compensator for removing nonlinear distortion. The compensator operates in a digital post-compensation configuration for linearization of devices or systems such as analog-to-digital converters and RF receiver electronics. The compensator also operates in a digital pre-compensation configuration for linearization of devices or systems such as digital-to-analog converters, RF power amplifiers, and RF transmitter electronics. The multi-dimensional compensator effectively removes linear and nonlinear distortion in these systems by accurately modeling the state of the device by tracking multiple functions of the input, including but not limited to present signal value, delay function, derivative function (including higher order derivatives), integral function (including higher order integrals), signal statistics (mean, median, standard deviation, variance), covariance function, power calculation function (RMS or peak), or polynomial functions. The multi-dimensional compensator can be adaptively calibrated using simple arithmetic operations that can be completed with low processing requirements and quickly to track parameters that rapidly change over time, temperature, power level such as in frequency-hopping systems.

The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain. In the present disclosure, a capacitor voltage coefficient can be extracted based on INL and the capacitor voltage coefficient is calibrated at a digital backend without adding an analog calibration circuit, thereby improving conversion accuracy of the ADC.