The present application provides a block copolymer and uses thereof. The block copolymer of the present application exhibits an excellent self-assembling property or phase separation property, can be provided with a variety of required functions without constraint and, especially, etching selectivity can be secured, making the block copolymer effectively applicable to such uses as pattern formation.

The present application provides a block copolymer and uses thereof. The block copolymer of the present application exhibits an excellent self-assembling property or phase separation property, can be provided with a variety of required functions without constraint and, especially, etching selectivity can be secured, making the block copolymer effectively applicable to such uses as pattern formation.

The present application provides a block copolymer and uses thereof. The block copolymer of the present application exhibits an excellent self-assembling property or phase separation property, and can be provided with a variety of required functions without constraint.

The present application relates to a monomer, a method for preparing a block copolymer, a block copolymer, and uses thereof. Each monomer of the present application exhibits an excellent self-assembling property and is capable of forming a block copolymer to which a variety of required functions are granted as necessary without constraint.

A method for manufacturing a semiconductor structure includes: providing a substrate, a bottom protecting wall being formed in the substrate; forming a mask layer on the substrate; forming a groove in the mask layer, a non-zero angle existing between a sidewall of the groove and a sidewall of the bottom protecting wall, and the bottom of the groove extending into the substrate; and forming a top protecting wall in the groove, the top protecting wall being in direct contact with the bottom protecting wall.

The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

[Problem]

To provide a composition capable of improving surface roughness of resist patterns, and also to provide a pattern formation method employing the composition.

[Solution]

The present invention provides a composition containing a particular nitrogen-containing compound, an anionic surfactant having a sulfo group, and water; and also provides a pattern formation method containing a step of applying the composition to a resist pattern beforehand developed and dried.

Provided is a method of manufacturing a patterned substrate. The method may be applied to a process of manufacturing a device such as an electronic device or integrated circuit, or another use, for example, to manufacture an integrated optical system, a guidance and detection pattern of a magnetic domain memory, a flat panel display, a LCD, a thin film magnetic head or an organic light emitting diode, and used to construct a pattern on a surface to be used to manufacture a discrete tract medium such as an integrated circuit, a bit-patterned medium and/or a magnetic storage device such as a hard drive.

Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.

A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.