A header, with improved cooling for electronic components for radio frequency signal transmission, for an electronic component for radio frequency data transfer, includes: a metallic base body including a plurality of electrical feedthroughs; a thermoelectric cooling element having one side bearing on the base body and an opposite side for mounting the electronic component; a radio frequency line to the electronic component being on the side for mounting the electronic component, with a ground conductor that is electrically connected to the metallic base body, the electrical connection to the metallic base body including a telluride element.

A laser element includes a light emitting portion that has at least two or more light emitting points, and a terminal member on which the light emitting portion is mounted. The terminal member includes a base portion that has a mounting surface on which the light emitting portion is mounted, a base that has a front surface where the base portion is provided substantially at a center, and four pins that extend from a rear surface of the base. The light emitting portion is positioned in a range surrounded by the four pins as viewed from the front surface of the base.

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

A stem for a semiconductor package, includes a plate, a frame, positioned on an outer periphery of the plate in a plan view, and bonded to the plate, and a lead terminal held in a state insulated from the plate and the frame. The plate protrudes from a top surface and a bottom surface of the frame, and a protruding amount of the plate from the top surface and a protruding amount of the plate from the bottom surface are the same.

A stem for a semiconductor package, includes a plate, a frame, positioned on an outer periphery of the plate in a plan view, and bonded to the plate, and a lead terminal held in a state insulated from the plate and the frame. The plate protrudes from a top surface and a bottom surface of the frame, and a protruding amount of the plate from the top surface and a protruding amount of the plate from the bottom surface are the same.

A device comprises a first sealing member, a second sealing member, a first circuit member and a second circuit member. The first sealing member comprises, as a base thereof, a first film formed of a film and comprises a conductive portion made of conductor. The device is formed with a closed space. The closed space is enclosed by the first sealing member and the second sealing member and is shut off from an outer space located outside the device. The first circuit member and the second circuit member are shut in the closed space and comprise a first contact point and a second contact point, respectively. At least one of the first circuit member and the second circuit member comprises an electrode. The conductive portion is in contact with the electrode in the closed space and is partially exposed to the outer space located outside the device.

A header for electronic components is provided. The header has a base with at least two electrical feedthroughs each having a feedthrough pin extending through the base and being electrically isolated to the base within the feedthrough. The further includes at least one pedestal connected to the base and two submounts. Each submount includes a carrier with a structured conductor plating that has at least two conductor traces with one of the conductor traces of each submount being electrically connected to one of the feedthrough pins. The submounts are equally formed but mounted in different orientations.

A header for an electronic component is provided. The header includes a base, a pedestal, and a submount. The base has a feedthrough with a feedthrough pin extending through the base and being electrically insulated from the base. The pedestal is connected to the base. The submount is connected to the pedestal. The pedestal is joined to the base via a pedestal substance-to-substance bond.

A header for a semiconductor device, includes a main body section having an upper surface, and a cavity formed in the upper surface, a heat dissipation section provided on the upper surface of the main body section, and a wiring board provided inside the cavity. The wiring board includes a substrate having a first principal surface, and a second principal surface provided on an opposite side from the first principal surface, a first conductor pattern provided on the first principal surface, and having a mounting section on which a semiconductor element is mounted, and a second conductor pattern provided on the second principal surface, and bonded to an inner wall surface of the cavity and the heat dissipation section. A portion of the first conductor pattern extends beyond the heat dissipation section when viewed in a thickness direction of the wiring board.