Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region.

Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region.

An electronic component mounting package includes a dielectric substrate between first portions of a pair of signal terminals that protrude from one side in a thickness direction from a first face of a base body. This dielectric substrate has a height lower than a height of the first portions. When an electronic component is mounted, a bonding wire is connected to a tip of each of the first portions to electrically connect the first portion to the electronic component.

Provided is a semiconductor laser device having enhanced heat dissipation properties. A semiconductor laser device 10 comprises a stem 11, a cap 12 that is attached to an upper surface of the stem 11, a semiconductor laser element 13, and a power-feeding member 14 that is at least partially buried in the stem 11. The power-feeding member 14 comprises an element-side terminal 32 that is electrically connected to the semiconductor laser element 13, and an external terminal 33. The external terminal 33 of the power-feeding member 14 is exposed on a side surface or the upper surface of the stem 11, and an attaching surface 11b that is attached to a mounting object is provided in a lower surface of the stem 11.

A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.

A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.

A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base.

A semiconductor package includes a flat plate-shaped terminal integrally formed with a housing portion for a semiconductor chip and a rod-shaped terminal pin that penetrates through a through-hole of the plate-shaped terminal. On a surface of the plate-shaped terminal, a resin guide portion for guiding the terminal pin to the through-hole of the plate-shaped terminal is provided. The resin guide portion is a portion of the housing portion and has a through-hole that is continuous with the through-hole of the plate-shaped terminal. During assembly of the semiconductor package, the terminal pin is inserted into the through-hole of the plate-shaped terminal, via the through-hole of the resin guide portion. A sidewall of the through-hole of the resin guide portion and a sidewall of the through-hole of the plate-shaped terminal have a same slope and form a single continuous surface; a border between the through-hole of the resin guide portion and the through-hole of the plate-shaped terminal is free of any step.

A device includes a hermetically sealed case with electronic circuitry housed within. One surface of the hermetically sealed case includes a metallic plate and a co-fired ceramic electrical feedthrough with a number of vias. The co-fired ceramic electrical feedthrough is hermetically joined to the metallic plate and a hybrid circuit is connected to the feedthrough.

A packaged power transistor device includes a Direct-Bonded Copper (DBC) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.