A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The method also includes forming a solder layer over the conductive pillar. The method further includes forming a water-soluble flux over the solder layer. In addition, the method includes reflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed.

The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.

Embodiments relate to a semiconductor structure and a fabrication method thereof. The semiconductor structure includes: a substrate, the substrate including a peripheral region and a chip region; a first dielectric layer positioned on the peripheral region and the chip region of the substrate; and a protective structure and a functional structure respectively positioned in the first dielectric layer on the peripheral region and in the first dielectric layer on the chip region. The protective structure includes a first subportion, a second subportion and a third subportion stacked in sequence, and the functional structure includes a fourth subportion and a fifth subportion stacked in sequence. A total height of the first subportion, the second subportion and the third subportion is equal to a total height of the fourth subportion and the fifth subportion.

A semiconductor device includes a substrate, a nitride semiconductor layer formed on the substrate, a source electrode and a drain electrode formed in the nitride semiconductor layer. The source electrode and drain electrode are arranged side by side in a first direction. A gate electrode is formed on the nitride semiconductor layer between the source electrode and the drain electrode. A first protective film is formed on the nitride semiconductor layer, and covers the first protective film covering the source electrode, the drain electrode, and the gate electrode. A source field plate is formed on the first protective film between the gate electrode and the drain electrode in a plan view. A dielectric-breakdown inhibition portion includes a part positioned between an end of the source field plate and an end of the drain electrode in a sectional view, and inhibits dielectric breakdown of the first protective film.

A semiconductor device includes a substrate, a pad disposed on the substrate, a passivation disposed over the substrate, a post passivation interconnection (PPI) disposed over the passivation and the substrate, a conductive line isolated from the PPI, a bump disposed on the PPI and a polymeric composite between the PPI and the conductive line, wherein the polymeric composite includes a first layer conformal to the conductive line and PPI and a second layer filling a gap between the PPI and the conductive line. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a passivation over the substrate, forming a post passivation interconnect (PPI) and a conductive line over the passivation, disposing a bump on the PPI, and forming a polymeric composite over the PPI by disposing a first layer conformal to the PPI and the conductive line and disposing a second layer to fill a gap between the PPI and the conductive line.

A power device includes a substrate, a drift layer disposed on the substrate, a terminal region and an active region disposed in the drift layer, an electrode layer disposed on the active region, a Schottky contact layer disposed between the electrode layer and the active region, a passivation layer disposed on the drift layer, and an isolation layer disposed between the passivation layer and the electrode layer so that the passivation layer and the electrode layer are at least partially separated from each other. The isolation layer, the electrode layer, and the passivation layer each respectively has a thermal expansion coefficient a, b, c, and a>b>c.

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10.sup.−6 m.) and approximately 10 micron (10.sup.−5 m.) from each one of said converging sides landing on an underlying metal layer.