A wiring board includes an electrical isolator laterally surrounded by a base board and a molding compound. The electrical isolator is inserted into a through opening of the base board and has a thickness greater than that of the base board. The molding compound covers the top side of the base board and sidewalls of the electrical isolator, and provides a reliable interface for deposition of a routing circuitry thereon. The base board can serve as an alignment guide for isolator placement or/and provide another routing to enhance electrical routing flexibility for the wiring board.

A semiconductor device includes a first conductive layer with first and second sections separated in a first direction. A first chip is on the first section and has a first, second and third electrodes. A second chip is on the second section and has a fourth and fifth electrode. A second conductive layer is between the sections of the first conductive layer in the first direction. The second conductive layer has a first connected section to which the second electrode is connected, a second connected section to which to the fifth electrode is connected, and a first clearance portion between the first and second connected sections in the first direction. A third conductive layer is spaced from the first conductive layer and the second conductive layer and is connected to the third electrode.

A thermal conductive structure and an electronic device are provided. The thermal conductive structure includes a thermal conductive metal layer and a structural layer. The structural layer is disposed on the thermal conductive metal layer. The structural layer is a stacked structure formed by a graphene layer and a ceramic material layer, or the structural layer is a graphene-mixed ceramic material layer. The thermal conductive structure can quickly conduct the heat energy generated by the heat source to the outside, thereby improving the heat dissipation performance of the electronic device.

A semiconductor package structure includes a chip, a first conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with a first metal electrode pad and a second side with a second metal electrode pad. The first conductive pillar is disposed adjacent to the chip. The dielectric layer covers the chip and the first conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the first conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the first conductive pillar. The second patterned conductive layer is disposed on a first surface of the dielectric.

A negative thermal expansion material and a preparation method thereof, and a negative thermal expansion film and a preparation method thereof are provided. The negative thermal expansion material includes Eu.sub.0.85Cu.sub.0.15MnO.sub.3-δ, wherein 0≤δ≤2.

A two-pack curable composition set having: a first agent comprising an organopolysiloxane having a branched structure and having a vinyl group at least at an end or in a side chain, a thermally conductive filler, a silica powder, and a platinum catalyst, and having a viscosity at 25° C. at a shear rate of 10 s.sup.−1 of 20 to 150 Pa.Math.s; and a second agent comprising an organopolysiloxane having a branched structure and having a vinyl group at least at an end or in a side chain, and a polydimethylsiloxane having a hydrosilyl group at least at an end or in a side chain, a thermally conductive filler, and a silica powder, and having a viscosity at 25° C. at a shear rate of 10 s.sup.−1 of 20 to 150 Pa.Math.s.

A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material.

A semiconductor substrate includes a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer includes a first material having a thermal conductivity of between 25 and 180 W/mK, and an insulation strength of between 15 and 50 kV/mm, and an electrically conducting or semiconducting second material evenly distributed within the first material.

An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.