A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

A capping layer is on top of a substrate. A first low-k dielectric layer is on top of the capping layer. One or more trenches are within the first low-k dielectric layer. Each of the one or more trenches have a same depth. Each trench of the one or more trenches include a barrier layer on top of the first low-k dielectric layer, a liner layer and a metal layer on top of the liner layer.

A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first electrode including a first vertical column, and a first bottom branch unit at a first vertical level and including a first set of bottom plates extending from the first vertical column and parallel to a first direction; two second electrodes respectively including a second vertical column, and a second bottom branch unit at a second vertical level higher than the first vertical level and including a first set of bottom plates extending from the second vertical column and parallel to the first direction; and a first insulation layer positioned between the first and second bottom branch unit. The first sets of bottom plates of the first and second bottom branch unit are partially overlapped. The first insulation layer and the first and second electrode together configure a programmable structure.

A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, a first gate electrode and a second gate electrode over the substrate and extending in a second direction, the semiconductor fin extending through the second gate electrode and terminating on the first gate electrode at one end of the semiconductor fin, and a first gate spacer and a second gate spacer laterally surrounding the first gate electrode and the second gate electrode, respectively. The one end of the semiconductor fin is surrounded by the first gate electrode. The first gate spacer includes a top substantially at a same height of a top of the second gate spacer.

A high writing rate antifuse array includes at least one sub-memory array including two antifuse memory cells arranged side by side between two neighboring bit lines. Each of two antifuse memory cells includes an antifuse transistor. The antifuse transistor has at least one sharp corner overlapping an antifuse gate above a first gate dielectric layer. Each of two antifuse memory cells includes a selection transistor. The second gate dielectric layers of two selection transistors are connected with each other. Thus, two antifuse memory cells are connected with the same select line and the same word line but are respectively connected with different bit lines. In the present invention, a common source contact is used, and two selection transistors share a channel, whereby to stabilize the source structure, increase the channel width of the selection transistors, and raise the writing rate without increase of overall area of the layout.

A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

The present disclosure provides a semiconductor device with a copper-manganese liner and a method for preparing the semiconductor device. The semiconductor device includes a first well region and a second well region disposed in a semiconductor substrate. The semiconductor device also includes a first dielectric layer disposed over the semiconductor substrate and covering the first well region and the second well region, and a gate structure disposed over the first dielectric layer and between the first well region and the second well region. The semiconductor device further includes a conductive structure disposed over and separated from the first well region by a portion of the first dielectric layer. The conductive feature includes a barrier layer and a conductive plug disposed over the barrier layer, and the barrier layer is made of copper-manganese (CuMn). The first well region, the conductive structure and the portion of the first dielectric layer form an anti-fuse structure.

A short-circuit switching device, in particular a bypass switch, includes a semiconductor element with at least one p-n junction and at least one pyrotechnic ignition device. The semiconductor element is or at least can be in a blocking state prior to the ignition of the pyrotechnic ignition device on the basis of the involvement of the p-n junction. After the ignition of the pyrotechnic ignition device, the semiconductor element is at least partially destroyed, namely at least with respect to the at least one p-n junction, and made at least partially conductive independently of the current flow direction by using explosion gas released by the ignition device after an explosion.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).