Gallium nitride (GaN) layer transfer for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A first layer including gallium and nitrogen is over a first region of the substrate, the first layer having a gallium-polar orientation with a top crystal plane consisting of a gallium face. A second layer including gallium and nitrogen is over a second region of the substrate, the second layer having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.

A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.

An electronic device, and method of producing an electronic device, are disclosed. The electronic device comprises a diamond substrate 10. Within the substrate 10 is an electrode 12, known as a ‘buried electrode’. A first surface 14 of the substrate 10 is provided with a conductive contact region 16. The electrode 12 is electrically connected to the contact region 16 by a conductive pillar 18. The electrode, conductive pillar, and contact region comprise modified portions of the diamond substrate, for example comprising at least one of graphitic carbon, amorphous carbon, and a combination of SP2 and SP3 phases of carbon, formed from a portion of diamond substrate.

The present disclosure provides a driving circuit, a driving IC, and a driving system, relating to the technical field of electronic circuits. The driving circuit comprises a control module and a driving signal output module, the control module is electrically connected to the driving signal output module, and the driving signal output module is configured to be electrically connected to a to-be-driven device, wherein the driving signal output module comprises at least two transistors, and the at least two transistors are epitaxially grown on the same substrate; and the control module is configured to control a closed state of the at least two transistors, so as to control an operation state of the to-be-driven device.

A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.

CMOS Systems formed in Wide Bandgap Semiconductor and involving use of a material that forms a rectifying junction with either N and P-type Field Induced Semiconductor, in combination with, preferably, Parallel and Adjacent Channels subject to control by a Gate removed from said Channels by insulator.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A semiconductor apparatus includes a plurality of semiconductor devices with a single substrate, a plurality of trench regions, each trench region including a trench, wherein the single substrate includes a substrate layer, a first epitaxial layer of a first conductivity type, disposed on the substrate layer, and a second epitaxial layer of a second conductivity type, disposed on the first epitaxial layer, wherein each trench of the plurality of trench regions extends through the second epitaxial layer and into the first epitaxial layer, thereby isolating adjacent semiconductor devices of the plurality of semiconductor devices.

The present invention relates to a semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series. One end of the first transistor structures and one end of the second transistor structures are jointly electrically connected to the drain structure of the power transistor structure, and the other end of the first transistor structures and the other end of the second transistor structures are jointly electrically connected to the source structure of the power transistor structure.

A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.