A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.

A photonic integrated circuit device includes a semiconductor substrate (e.g., wafer) having a chip region therein, which is bounded on at least one side thereof by a scribe line. The chip region includes an optical transmitter, an optical receiver and a test optical waveguide. This test optical waveguide is coupled to the optical transmitter and the optical receiver and overlaps the scribe line. During a substrate dicing operation, a portion of the test optical waveguide overlapping the scribe line is removed.

A photonic integrated circuit device includes a semiconductor substrate (e.g., wafer) having a chip region therein, which is bounded on at least one side thereof by a scribe line. The chip region includes an optical transmitter, an optical receiver and a test optical waveguide. This test optical waveguide is coupled to the optical transmitter and the optical receiver and overlaps the scribe line. During a substrate dicing operation, a portion of the test optical waveguide overlapping the scribe line is removed.

A photonic integrated circuit device includes a semiconductor substrate (e.g., wafer) having a chip region therein, which is bounded on at least one side thereof by a scribe line. The chip region includes an optical transmitter, an optical receiver and a test optical waveguide. This test optical waveguide is coupled to the optical transmitter and the optical receiver and overlaps the scribe line. During a substrate dicing operation, a portion of the test optical waveguide overlapping the scribe line is removed.

A member is provided which includes a silicon base substrate layer, a transition layer arranged over the silicon base substrate layer, and a gallium nitride (GaN) buffer layer arranged over the transition layer. The member further includes a gallium oxide layer. The member is beneficial for co-integration of ultra-wide-bandgap technology with wide bandgap technology, such as by using the gallium oxide layer with the gallium nitride buffer layer on cheap silicon substrates, such as the silicon base substrate layer. Therefore, the member provides access to establish the gallium nitride buffer layer (or gallium nitride) on the silicon base substrate layer (or silicon production lines) with improved thermal conductivity and higher electrical performance.

A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode.

A high-voltage capacitor structure comprises a capacitor. The capacitor includes a substrate, a field oxidation layer, an active region, a dielectric layer, a passivation layer and a metal layer. The field oxidation layer is disposed above the substrate. The active region is disposed above the substrate or in the substrate. The dielectric layer is disposed above the active region and the field oxidation layer. The passivation layer is disposed above the dielectric layer. The metal layer is disposed above the passivation layer. The metal layer and the active region serve as a first electrode and a second electrode of the capacitor, respectively, wherein the active region is disposed below the dielectric layer. Some embodiments provide a digital isolation apparatus comprising at least one high-voltage isolator, each of which includes the above high-voltage capacitor structure.

Certain aspects of the present disclosure are generally directed to an integrated circuit device. The integrated circuit device generally includes a capacitive element, a first switch having a first terminal coupled to a first terminal of a capacitive element, and a second switch coupled between the first terminal and a second terminal of the capacitive element in the integrated circuit device.

A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode.

A method of fabricating a semiconductor product including processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the wafer. Backside processing of the wafer includes forming implantations from the backside, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.