A display device includes: a substrate; a display area including pixels arranged on the substrate; a first area disposed at one side of the display area; a second area including pads arranged on the substrate; a bending area disposed between the first area and the second area; and a fan-out line disposed in the first area, the bending area, and the second area. The fan-out line includes: a plurality of sub-routing lines arranged in the first area and electrically connected to each other; and a plurality of sub-pad lines arranged in the second area and electrically connected to each other. The number of the plurality of sub-routing lines is greater than the number of the plurality of sub-pad lines.

A semiconductor device having favorable and stable electrical characteristics is provided. The semiconductor device includes a first and a second transistor over an insulating surface. The first and the second transistors each include a first insulating layer, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a first conductive layer overlapping with the semiconductor layer with the second insulating layer interposed therebetween. The first insulating layer includes a convex first region that overlaps with the semiconductor layer and a second region that does not and is thinner than the first region. The first conductive layer includes a part over the second region where a lower surface of the first conductive layer is positioned below a lower surface of the semiconductor layer. The second transistor further includes a third conductive layer overlapping with the semiconductor layer with the first insulating layer interposed therebetween.

A display device having an improved display characteristics and reduced manufacturing cost is provided. The display device includes a plurality of pixels arranged on a surface of a substrate. The plurality of pixels each include: a light-emitting element; a driving transistor; a selecting transistor; and a retention capacitor. The driving transistor has a bottom-gate structure. The driving transistor has a semiconductor layer containing a first semiconductor. The retention capacitor has a first electrode and a second electrode. The first electrode doubles as a gate of the driving transistor. The second electrode is disposed at a lower layer than the first electrode and contains a second semiconductor.

An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, in the oxide semiconductor layer, in at least a part of a first region covered with the gate electrode with the gate insulating layer interposed therebetween, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film placed on the high mobility oxide semiconductor film and having a lower mobility than the high mobility oxide semiconductor film is provided, and in the second TFT, in a first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided, and the other oxide semiconductor film is not provided.

A display apparatus includes a substrate including a display area and a peripheral area outside the display area, a pixel circuit disposed on the substrate in the display area, where the pixel circuit includes a driving thin film transistor and a switching thin film transistor, and a display element connected to the pixel circuit. The driving thin film transistor includes a driving semiconductor layer having a single layer structure, the switching thin film transistor includes a switching semiconductor layer in which a first layer, a second layer, and a third layer, which are oxide semiconductors, are sequentially stacked one on another, and a conductivity of the second layer of the switching semiconductor layer is greater than respective conductivities of the first layer and the third layer of the switching semiconductor layer.

A display device includes a substrate and a pixel layer disposed on the substrate. The pixel layer includes a circuit element layer having an opening. The circuit element layer includes a first semiconductor layer and a first conductive layer that includes a first scan line pattern and an emission control line. A second conductive layer is disposed on the first conductive layer and includes a first initialization line, a second scan line pattern and a third scan line pattern. A second semiconductor layer is disposed on the second conductive layer. A third conductive layer is disposed on the second semiconductor layer and includes fourth and fifth scan line patterns. The first initialization line includes a first portion and a second portion each extending in a first direction, and a third portion disposed therebetween. The second portion extends diagonally with respect to the first direction.

A semiconductor device in which variations in characteristics, deterioration of elements, and abnormality in shape are inhibited is provided. The semiconductor device includes a first region including a plurality of elements and a second region including a plurality of dummy elements. The second region is provided in an outer edge of the first region, and the element and the dummy element each include an oxide semiconductor. The element and the dummy element have the same structure, and a structure body included in the element and a structure body included in the dummy element are formed with the same material and provided in the same layer. The oxide semiconductor includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.

A display substrate, a preparation method and driving method therefor, and a display apparatus. The display substrate includes a substrate and a switch structure arranged on the substrate, the switch structure being electrically connected to a control signal terminal, a signal input terminal and a signal output terminal. The switch structure comprises a switching unit. The switching unit comprises a first transistor and a second transistor; and the types of the first transistor and the second transistor are opposite. The first transistor comprises: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor comprises: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

A clock and voltage generation circuit includes a voltage generator which generates a first gate high voltage, a first gate low voltage, a second gate high voltage, and a second gate low voltage, a first level shifter which generates a first gate clock signal which swings between the first gate high voltage and the first gate low voltage in synchronization with a gate pulse signal, and a second level shifter which generates a second gate clock signal which swings between the second gate high voltage and the second gate low voltage in synchronization with the gate pulse signal. The voltage generator lowers the second gate high voltage to a voltage level of a kickback reference voltage in response to a kickback signal, and the first gate low voltage and the second gate high voltage are gate-on voltages, and the first gate high voltage and the second gate low voltage are gate-off voltages.

A display device includes a polycrystalline semiconductor including a channel and electrodes of a driving transistor; a gate electrode of the driving transistor on the channel of the driving transistor; a first storage electrode on the gate electrode of the driving transistor; a light blocking layer of a first transistor and a light blocking layer of a second transistor; an oxide semiconductor including a channel and electrodes of the first transistor, and a channel and electrodes of the second transistor; a gate electrode of the first transistor on the channel of the first transistor; and a gate electrode of the second transistor on the channel of the second transistor. The light blocking layer of the first transistor and the first storage electrode are on a same layer, and the light blocking layer of the second transistor and the gate electrode of the driving transistor are on a same layer.