Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

P-N diodes that include p-type doped diamond and devices, such as p-n-p heterojunction bipolar transistors, that incorporate the p-n diodes are provided. In the p-n diodes, the diamond at the p-n junction has a positive electron affinity and is passivated by a thin layer of inorganic material that provides a tunneling layer that passivates the bonding interface states, without hindering carrier transport across the interface.

A semiconductor structure having a multiple-porous graphene layer includes a sapphire substrate, a single or multiple layer porous graphene film, and a gallium nitride layer. A fabrication method for forming the semiconductor structure having a single or multiple layer porous graphene film, includes: firstly, growing up the graphene on the copper foil; then, using the acetone and isopropyl alcohol to wash the sapphire substrate, and then using the nitrogen flow to dry up; transferring the graphene onto the semiconductor substrate, using the Poly(methyl methacrylate) to fix the single or multiple layer porous graphene film, and using the acetone to wash up; using the photolithography process to etch the whole surface of the multiple-porous graphene layer; and, using the metalorganic chemical vapor deposition to deposit gallium nitride on the single or multiple layer porous graphene film and the sapphire substrate.

An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

Techniques for integrating a self-aligned heterojunction for TFETs in a vertical GAA architecture are provided. In one aspect, a method of forming a vertical TFET device includes: forming a doped SiGe layer on a Si substrate; forming fins that extend through the doped SiGe layer and partway into the Si substrate such that each of the fins includes a doped SiGe portion disposed on a Si portion with a heterojunction therebetween, wherein the SiGe portion is a source and the Si portion is a channel; selectively forming oxide spacers, aligned with the heterojunction, along opposite sidewalls of only the doped SiGe portion; and forming a gate stack around the Si portion and doped SiGe that is self-aligned with the heterojunction. A vertical TFET device formed by the method is also provided.

An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

Disclosed is a graphene-based ternary barristor using a Schottky junction graphene semiconductor. A graphene channel layer is doped with N-type and N-type dopants to have two different Fermi levels and form a PN junction. Accordingly, a voltage is applied to a gate electrode layer to move the Fermi levels of the graphene channel layer and adjust the height of the Schottky barrier, thus generating current. Also, the height of the Schottky barrier is adjusted depending on the doping concentration of the graphene channel That is, the height of the Schottky barrier is changed depending on the applied gate voltage, and thus the flow of current is changed. Also, it is possible to adjust the height of the Schottky barrier by adjusting the doping concentration of the graphene channel. Accordingly, since the graphene-based ternary barristor has a high current ratio by adjusting a gate voltage, the graphene-based ternary barristor may be applied to a logic circuit.

Structures for a field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer. The gate conductor layer has a first portion disposed above the top surface of the semiconductor substrate and a second portion disposed inside the trench below the top surface of the semiconductor substrate.

A field effect transistor and a manufacturing method thereof are provided. The field effect transistor includes two top gate structures (1031C and 1031D) and two bottom gate structures (1032A and 1032B). The top gate structures (1031C and 1031D) and the bottom gate structures (1032A and 1032B) are opposite to each other in pair. This increases a quantity of control-voltage-induced carriers in the field effect transistor, and therefore increases an output current of the field effect transistor, improves a power gain limit frequency in high-frequency use, and makes an electric field between the top gate structures (1031C and 1031D) and the bottom gate structures (1032A and 1032B) more adequately cover a channel layer (106) between source structures (1041 and 1042) and a drain (105), thereby reducing a parasitic effect in a high frequency, and further improving a frequency characteristic of the field effect transistor.

Provided is a semiconductor device according to an embodiment including an i-type or first-conductivity-type first diamond semiconductor layer having a first side surface, a second-conductivity-type second diamond semiconductor layer provided on the first diamond semiconductor layer and having a second side surface, a third diamond semiconductor layer being in contact with the first side surface and the second side surface, the third diamond semiconductor containing nitrogen, a first electrode electrically connected to the first diamond semiconductor layer, and a second electrode electrically connected to the second diamond semiconductor layer.