A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

A package base substrate includes a base layer; a plurality of lower surface connection pads disposed on a lower surface of the base layer; a plurality of lower surface wiring patterns disposed on a lower surface of the base layer and respectively connected to a set of lower surface connection pads of the plurality of lower surface connection pads; and a lower surface solder resist layer covering a portion of each of the plurality of lower surface connection pads and the plurality of lower surface wiring patterns on a lower surface of the base layer, wherein each of at least some of the lower surface connection pads of the set of lower surface connection pads has a teardrop shape in a plan view, and includes a ball land portion having a planar circular shape, including a terminal contact portion exposed without being covered by the lower surface solder resist layer, and an edge portion surrounding the terminal contact portion and covered by the lower surface solder resist layer; and a connection reinforcement portion between the ball land portion and the lower surface wiring pattern, including an extension line portion having a width that is the same as a line width of the lower surface wiring pattern and extending from the ball land portion to the lower surface wiring pattern, and a corner reinforcement portion filling a corner between the ball land portion and the extension line portion, and wherein an extension length of the extension line portion has a value greater than a radius of the terminal contact portion.

A semiconductor device includes a pad formed on a surface of a substrate, a bonding wire for connecting the pad to an external circuit, and a resin layer covering at least a connection portion between the pad and the bonding wire and exposing at least a part of the substrate outside the pad.

A semiconductor device includes: a metal block; a semiconductor element fixed to an upper surface of the block with a first joining material; a main terminal fixed to an upper surface of the element with a second joining material; a signal terminal electrically connected to the element; and a mold resin covers the element, the first and second joining materials, a part of the block, of the main and signal terminals. In the element, a current flows in a longitudinal direction. A lower surface of the block is exposed from the resin. The main and the signal terminals are exposed from a side surface of the resin. The main terminal has a first portion in the resin, a second portion continuous with the first portion and bent downward outside the resin, and a third portion continuous with the second portion and substantially parallel to a lower surface of the resin.

A semiconductor package including a first lower stack on a substrate and including first lower semiconductor chips, a redistribution substrate on the first lower stack, a redistribution connector electrically connecting the substrate to the redistribution substrate, a first upper stack on the redistribution substrate and including first upper semiconductor chips, a first upper connector electrically connecting the redistribution substrate to the first upper stack, a second upper stack horizontally spaced apart from the first upper stack and including second upper semiconductor chips, and a second upper connector electrically connecting the redistribution substrate to the second upper stack may be provided. The redistribution connector may be on one side of the redistribution substrate. The first upper connector may be on one side of the first upper stack. The second upper connector may be on one side of the second upper stack.

A semiconductor assembly includes a first die and a second die. The semiconductor assembly also includes a film on die (FOD) layer configured to attach the first die to the second die. The FOD layer is disposed on a first surface of the first die. The FOD layer includes a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface. The FOD layer also includes a second portion that includes a second DAF disposed on a peripheral region of the first surface surrounding the inner region. The second DAF includes a different material than the first DAF.

Provided is a semiconductor package having a package housing in an engraved surface form and a method of manufacturing the same, wherein the semiconductor package includes: at least one substrate on which at least one semiconductor chip is installed; at least one terminal lead electrically connected to the substrates; electrical connectors for connecting the semiconductor chips to the substrates or the terminal leads; a package housing covering the semiconductor chips, the electrical connectors, and the at least one substrate; at least one stopper which is formed of a material same as that of the package housing, is higher by a certain height than exposed surfaces of the substrates, is disposed on the exposed surfaces of the substrates, or covers at least a part of the exposed surfaces; and at least one heat sink transmitting heat from the semiconductor chips and radiating heat, wherein the at least a part of the exposed surfaces of the at least one substrate is formed on the upper surface, the lower surface, or the upper and lower surfaces of the package housing and the exposed surfaces of the at least one substrate are joined to the heat sinks by using heat transfer connectors interposed therebetween. Accordingly, the full thickness of the heat transfer connectors may be uniformly maintained.

Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A semiconductor package includes a lower semiconductor chip, a first upper semiconductor chip including upper pads, and bonding wires coupled to the substrate and the upper pads. The first upper semiconductor chip has a first overhang region adjacent to a first lateral surface of the first upper semiconductor chip, a second overhang region adjacent to a second lateral surface of the first upper semiconductor chip, and a first corner overhang region adjacent to a corner where the first and second lateral surfaces meet with each other. The upper pads include first upper pads on the first overhang region and second upper pads on the second overhang region. The number of the first upper pads is less than that of the second upper pads. The upper pads are spaced apart from the first corner overhang region.