Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.

The invention provides a chemical-mechanical polishing composition comprising: (a) colloidal silica particles that are surface modified with metal ions selected from Mg, Ca, Al, B, Be, and combinations thereof, and wherein the colloidal silica particles have a surface hydroxyl group density of from about 1.5 hydroxyls per nm.sup.2 to about 8 hydroxyls per nm.sup.2 of a surface area of the particles, (b) an anionic surfactant, (c) a buffering agent, and (d) water, wherein the polishing composition has a pH of about 2 to about 7, and wherein the polishing composition is substantially free of an oxidizing agent that oxidizes a metal. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains silicon nitride, silicon oxide, and/or polysilicon.

Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess.

Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess.

A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

The dry etching method of the present invention etches a metal film formed on a surface of a workpiece by bringing etching gases each containing a β-diketone into contact with the metal film. The method includes: a first etching step of bringing a first etching gas containing a first β-diketone into contact with the metal film; and a second etching step of bringing a second etching gas containing a second β-diketone into contact with the metal film after the first etching step. The first β-diketone is a compound capable of forming a first complex through a reaction with the metal film. The second β-diketone is a compound capable of forming a second complex having a lower sublimation point than the first complex through a reaction with the metal film.

The dry etching method of the present invention etches a metal film formed on a surface of a workpiece by bringing etching gases each containing a β-diketone into contact with the metal film. The method includes: a first etching step of bringing a first etching gas containing a first β-diketone into contact with the metal film; and a second etching step of bringing a second etching gas containing a second β-diketone into contact with the metal film after the first etching step. The first β-diketone is a compound capable of forming a first complex through a reaction with the metal film. The second β-diketone is a compound capable of forming a second complex having a lower sublimation point than the first complex through a reaction with the metal film.

The CMP polishing liquid of the invention comprises a metal salt containing at least one type of metal selected from the group consisting of metals of Groups 8, 11, 12 and 13, 1,2,4-triazole, a phosphorus acid, an oxidizing agent and abrasive grains. The polishing method of the invention comprises a step of polishing at least a palladium layer with an abrasive cloth while supplying a CMP polishing liquid between the palladium layer of a substrate having the palladium layer and the abrasive cloth, wherein the CMP polishing liquid comprises a metal salt containing at least one type of metal selected from the group consisting of metals of Groups 8, 11, 12 and 13, 1,2,4-triazole, a phosphorus acid, an oxidizing agent and abrasive grains.

A polishing composition contains abrasive grains and water. 50% by mass or more of the abrasive grains consists of particles A having particle sizes between 40 nm and 80 nm inclusive, and 10% by mass or more of the abrasive grains consists of particles B having particle sizes between 150 nm and 300 nm inclusive. The polishing composition is used to polish a surface of a compound semiconductor substrate.

A polishing composition contains abrasive grains and water. 50% by mass or more of the abrasive grains consists of particles A having particle sizes between 40 nm and 80 nm inclusive, and 10% by mass or more of the abrasive grains consists of particles B having particle sizes between 150 nm and 300 nm inclusive. The polishing composition is used to polish a surface of a compound semiconductor substrate.