Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.

A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si.sub.1-yGe.sub.y, where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si.sub.1-xGe.sub.x, where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.

A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si.sub.1-yGe.sub.y, where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si.sub.1-xGe.sub.x, where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.

According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first metal portion, a third semiconductor region of a second conductivity type, a first electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on part of the second semiconductor region. The first metal portion is provided in the first semiconductor region. The third semiconductor region is positioned on the first portion. The fourth semiconductor region is provided on another part of the second semiconductor region. The fourth semiconductor region is separated from the third semiconductor region. The fourth semiconductor region is positioned on the second portion.

A substrate support device relating to technology disclosed in the description of the present application includes: a holding plate for opposing a substrate bowable by being heated by irradiation with flash light; and a plurality of substrate support pins provided on the holding plate and being for supporting the substrate, wherein the plurality of substrate support pins are arranged at locations where a volume of a space between the holding plate and the substrate in an unbowed state and a volume of a space between the holding plate and the substrate in a bowed state are equal to each other. Breakage of the substrate can be suppressed in a case where the substrate is bowed by flash light.

A substrate support device relating to technology disclosed in the description of the present application includes: a holding plate for opposing a substrate bowable by being heated by irradiation with flash light; and a plurality of substrate support pins provided on the holding plate and being for supporting the substrate, wherein the plurality of substrate support pins are arranged at locations where a volume of a space between the holding plate and the substrate in an unbowed state and a volume of a space between the holding plate and the substrate in a bowed state are equal to each other. Breakage of the substrate can be suppressed in a case where the substrate is bowed by flash light.

A silicon wafer having a layer of oxygen precipitates and method of manufacturing thereof wherein the wafer exhibiting robustness characterized as having a ratio of a first average density from a first treatment that to a second average density from a second treatment is between 0.74 to 1.02, wherein the first treatment includes heating the wafer or a portion of the wafer at about 1150° C. for about 2 minutes and then between about 950 to 1000° C. for about 16 hours, and the second treatment includes heating the wafer or a portion of the wafer at about 780° C. for about 3 hours and then between about 950 to 1000° C. for about 16 hours. The wafer exhibits heretofore unattainable uniformity wherein a ratio of an oxygen precipitate density determined from any one cubic centimeter in the BMD layer of the wafer to another oxygen precipitate density from any other one cubic centimeter in the BMD layer of the wafer is in a range of 0.77 to 1.30.

A silicon wafer having a layer of oxygen precipitates and method of manufacturing thereof wherein the wafer exhibiting robustness characterized as having a ratio of a first average density from a first treatment that to a second average density from a second treatment is between 0.74 to 1.02, wherein the first treatment includes heating the wafer or a portion of the wafer at about 1150° C. for about 2 minutes and then between about 950 to 1000° C. for about 16 hours, and the second treatment includes heating the wafer or a portion of the wafer at about 780° C. for about 3 hours and then between about 950 to 1000° C. for about 16 hours. The wafer exhibits heretofore unattainable uniformity wherein a ratio of an oxygen precipitate density determined from any one cubic centimeter in the BMD layer of the wafer to another oxygen precipitate density from any other one cubic centimeter in the BMD layer of the wafer is in a range of 0.77 to 1.30.

Aspects generally relate to methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers. In one aspect, film stress is altered while facilitating enhanced etch selectivity. In one implementation, a method of processing a substrate includes depositing one or more amorphous carbon hardmask layers onto the substrate, and conducting a rapid thermal anneal operation on the substrate after depositing the one or more amorphous carbon hardmask layers. The rapid thermal anneal operation lasts for an anneal time that is 60 seconds or less. The rapid thermal anneal operation includes heating the substrate to an anneal temperature that is within a range of 600 degrees Celsius to 1,000 degrees Celsius. The method includes etching the substrate after conducting the rapid thermal anneal operation.

Aspects generally relate to methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers. In one aspect, film stress is altered while facilitating enhanced etch selectivity. In one implementation, a method of processing a substrate includes depositing one or more amorphous carbon hardmask layers onto the substrate, and conducting a rapid thermal anneal operation on the substrate after depositing the one or more amorphous carbon hardmask layers. The rapid thermal anneal operation lasts for an anneal time that is 60 seconds or less. The rapid thermal anneal operation includes heating the substrate to an anneal temperature that is within a range of 600 degrees Celsius to 1,000 degrees Celsius. The method includes etching the substrate after conducting the rapid thermal anneal operation.