A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.

A semiconductor device includes a peripheral circuit region comprising a first substrate, circuit elements on the first substrate, a first insulating layer covering the circuit elements, and a contact plug passing through the first insulating layer and disposed to be connected to the first substrate; and a memory cell region comprising a second substrate, gate electrodes on the second substrate and stacked in a vertical direction, and channel structures passing through the gate electrodes, wherein the contact plug comprises a metal silicide layer disposed to contact the first substrate and having a first thickness, a first metal nitride layer on the metal silicide layer to contact the metal silicide layer and having a second thickness, greater than the first thickness, a second metal nitride layer on the first metal nitride layer, and a conductive layer on the second metal nitride layer.

Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

An interconnect structure of a semiconductor device includes a conductive via and a barrier layer lining an interface between a dielectric layer and the conductive via. The barrier layer is selectively deposited along sidewalls of a recess formed in a dielectric layer. The conductive via is formed by selectively electroplating electrically conductive material such as rhodium, iridium, or platinum in an opening of the recess, where the conductive via is grown upwards from an exposed metal surface at a bottom of the recess. The conductive via includes an electrically conductive material having a low electron mean free path, low electrical resistivity, and high melting point. The interconnect structure of the semiconductor device has reduced via resistance and improved resistance to electromigration and/or stress migration.

An integrated electronic device including: a main body delimited by a front surface; a top conductive region extending within the main body, starting from the front surface; a first dielectric region extending on the front surface; and a barrier structure, arranged on the first dielectric region. A first aperture extends through the barrier structure and the first dielectric region; the first aperture is delimited at bottom by the top conductive region. The integrated electronic device further includes a contact structure including at least a first conductive region extending within the first aperture, in direct contact with the top conductive region and the barrier structure.

A semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer. The height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and the distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layer correlates to the capacitance of each of the one or more backside metal layers.

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, an interlayer dielectric (ILD) layer disposed over the metal gate structure, and a gate contact disposed in the ILD layer and over the metal gate structure, where a bottom surface of the gate contact is defined by a barrier layer disposed over the metal gate structure, where sidewall surfaces of the gate contact are defined by and directly in contact with the ILD layer, and where the barrier layer is free of nitrogen.

Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a first conductive feature in a first dielectric layer, a second conductive feature aligned with and over the first conductive feature, a first insulation layer over the first dielectric layer and the second conductive feature, a second dielectric layer over the first insulating layer, and a contact via through the first insulation layer and the second dielectric layer.

A semiconductor device with an identification structure is provided. The semiconductor device includes a substrate and a metallization structure over the substrate. The metallization structure includes an interconnection region having a plurality of metal layers and an identification region isolated from the interconnection region. The identification region has an identification structure leveled with one of the metal layer. The identification structure includes at least one exposing recess and at least one exposing fuse. A method for manufacturing a semiconductor device with an identification structure and a method for tracing a production information of a semiconductor device are also provided.