H01L23/5328

Wafer level chip scale package interconnects and methods of manufacture thereof

A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.

Polymer member based interconnect

An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is coated with a conductive material (144). Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

Flexible LED display
09865646 · 2018-01-09 · ·

This present invention provides a flexible LED display by utilizing flexible wirings and the locations of the conductive pins on the bottom side of each single color LEDs or full color LEDs to make each of the single color LEDs or full color LEDs mount on each pixel defined by the flexible wires formed on the transparent flexible substrate, and this flexible LED display which characterizes in separating the wirings crossing over with each other by a so-called bridge technology and utilizing a single-layered substrate to save costs of processes and materials.

Integrated circuit package fabrication

A method of making an integrated circuit (IC) device includes forming a lead frame in a lead frame strip. Only portions of the lead frame are plated with a conductor. A die pad is attached to an unplated portion of said lead frame.

INTEGRATED CIRCUIT HAVING SLOT VIA AND METHOD OF FORMING THE SAME

An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line.

Anisotropic conductive material, electronic device including anisotropic conductive material, and method of manufacturing electronic device

Provided are anisotropic conductive materials, electronic devices including anisotropic conductive materials, and/or methods of manufacturing the electronic devices. An anisotropic conductive material may include a plurality of particles in a matrix material layer. At least some of the particles may include a core portion and a shell portion covering the core portion. The core portion may include a conductive material that is in a liquid state at a temperature greater than 15 C. and less than or equal to about 110 C. or less. For example, the core portion may include at least one of a liquid metal, a low melting point solder, and a nanofiller. The shell portion may include an insulating material. A bonding portion formed by using the anisotropic conductive material may include the core portion outflowed from the particle and may further include an intermetallic compound.

Pattern placement error compensation layer in via opening
09748176 · 2017-08-29 · ·

A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

Integrated circuit having slot via and method of forming the same

An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line.

Pattern placement error compensation layer
09704807 · 2017-07-11 · ·

A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

Gas Cushion Apparatus and Techniques for Substrate Coating

A coating can be provided on a substrate. Fabrication of the coating can include forming a solid layer in a specified region of the substrate while supporting the substrate in a coating system using a gas cushion. For example, a liquid coating can be printed over the specified region while the substrate is supported by the gas cushion. The substrate can be held for a specified duration after the printing the patterned liquid. The substrate can be conveyed to a treatment zone while supported using the gas cushion. The liquid coating can be treated to provide the solid layer including continuing to support the substrate using the gas cushion.