Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 ?A/?m.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

The proposed device includes a first chip (102) comprising a superconducting quantum bit and a second chip (104) bonded to the first chip, the second chip including a substrate (108) having first and second opposing surfaces. The first surface (101) facing the first chip includes a layer (105) of superconductor material which includes a first circuit element. The second chip further includes a second layer (107) on the second surface (103) which includes a second circuit element, and a through connector (109) that extends from the first surface to the second surface and electrically connects a portion of the superconductor material layer to the second circuit element.

Electrical, mechanical, computing, and/or other devices that include components formed of extremely low resistance (ELR) materials, including, but not limited to, modified ELR materials, layered ELR materials, and new ELR materials, are described.

A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

A method of forming a superconductor structure is provided. The method comprises forming a superconducting element in a first dielectric layer that has a top surface aligned with the top surface of the first dielectric layer, forming a second dielectric layer over the first dielectric layer and the superconducting element, and forming an opening in the second dielectric layer to a top surface of the superconducting element. The method also comprises performing a cleaning process on the top surface of the superconducting element to remove oxides formed on the top surface of the superconducting element at a first processing stage, forming a protective barrier over the top surface of the superconducting element, and moving the superconductor structure to a second processing stage for further processing.

A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a superconducting interconnect element in a first dielectric layer, such that the superconducting interconnect element has a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The method also includes performing a plasma clean on a top surface of the first interconnect layer, and depositing a second dielectric layer over the first dielectric layer.

A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

High temperature superconductor (HTS)-based interconnect systems comprising a cable including HTS-based interconnects are described. Each of the HTS-based interconnects includes a first portion extending from a first end towards an intermediate portion and a second portion extending from the intermediate portion to a second end. Each of the HTS-based interconnects includes a substrate layer formed in the first portion, in the intermediate portion, and in the second portion, a high temperature superconductor layer formed in at least a sub-portion of the first portion, in the intermediate portion, and in the second portion, and a metallic layer formed in the first portion and in at least a sub-portion of the intermediate portion. The HTS-based interconnect system includes a thermal load management system configured to maintain the intermediate portion of each of the HTS-based interconnects at a predetermined temperature in a range between a temperature of 60 kelvin and 92 kelvin.

An integrated circuit (IC) device includes a substrate having a fin-type active region extending in a first direction, a gate structure intersecting the fin-type active region on the substrate, the gate structure extending in a second direction perpendicular to the first direction and parallel to a top surface of the substrate, source and drain regions on both sides of the gate structure, and a first contact structure electrically connected to one of the source and drain regions, the first contact structure including a first contact plug including a first material and a first wetting layer surrounding the first contact plug, the first wetting layer including a second material having a lattice constant that differs from a lattice constant of the first material by about 10% or less.