An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO.sub.3(ZnO).sub.m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is inhibited and reliability is improved. The transistor includes a first gate electrode; a first insulating film over the first gate electrode; an oxide semiconductor film over the first insulating film; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode; and a second gate electrode over the second insulating film. The second insulating film includes oxygen. The second gate electrode includes the same metal element as at least one of metal elements of the oxide semiconductor film and has a region thinner than the oxide semiconductor film.

The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.

A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.

A pixel includes a pixel circuit and an organic light emitting diode. The pixel circuit has first, second, third, and fourth transistors. The first transistor controls an amount of current flowing from a first driving power supply coupled to a first node to a second driving power supply through the organic light emitting diode. The turns on when a scan signal is supplied to a first scan line. The third transistor turns on when a scan signal is supplied to a second scan line. The fourth transistor turns on when a scan signal is supplied to a third scan line. The first transistor is a p-type Low Temperature Poly-Silicon thin film transistor and the third transistor and the fourth transistor are n-type oxide semiconductor thin film transistors.

An array substrate, a fabrication method thereof, and a display panel are provided. The array substrate comprises a substrate, and a plurality of thin-film-transistors, which includes an active layer formed on the substrate including a source region, a drain region, and a channel region located between the source region and the drain region, a source electrode metal contact layer, a drain electrode metal contact layer, a barrier layer formed on a side of the active layer facing away from the substrate, a source electrode formed on a side of the source electrode metal contact layer facing away from active layer, a drain electrode formed on a side of the drain electrode metal contact layer facing away from the active layer, and a gate electrode insulated from the barrier layer and formed on a side of the barrier layer facing away from the active layer.

Disclosed is a power storage element including a positive electrode current collector layer and a negative electrode current collector layer which are arranged on the same plane and can be formed through a simple process. The power storage element further includes a positive electrode active material layer on the positive electrode current collector layer; a negative electrode active material layer on the negative electrode current collector layer; and a solid electrolyte layer in contact with at least the positive electrode active material layer and the negative electrode active material layer. The positive electrode active material layer and the negative electrode active material layer are formed by oxidation treatment.

A method for manufacturing an array substrate is provided. The array substrate, by providing a black matrix and a color resist layer on the array substrate and providing the color resist layer on the TFT layer, prevents bad influences on the color resist layer caused by a high temperature TFT process so as to provide a liquid crystal panel with improved displaying quality. The method includes, firstly, forming a black matrix on a substrate, and secondly, implementing a TFT manufacture process on the black matrix, and then forming a color resist layer after the TFT manufacture process. Accordingly, forming both the black matrix and the color resist layer on the array substrate can be achieved, where the color resist layer is formed after the TFT manufacture process to prevent bad phenomenon caused by the high temperature of the TFT process.

The present disclosure discloses an array substrate, a display device and manufacturing methods thereof. The array substrate comprises: a base, a gate metal layer, an active layer, a source/drain metal layer, and a pixel electrode layer, wherein the array substrate has a storage capacitor region; in the storage capacitor region, the gate metal layer, the active layer, the source/drain metal layer and the pixel electrode layer comprise respective patterns; wherein, the projections of the gate metal layer storage pattern, the active layer storage pattern, the source/drain metal layer storage pattern, and the pixel electrode layer storage pattern on the base at least partially overlap, and the pixel electrode layer storage pattern is electrically connected to the gate metal layer storage pattern to form a first electrode of the storage capacitor, the active layer storage pattern is electrically connected to the source/drain metal layer storage pattern to form a second electrode.