An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.

To provide a semiconductor device that holds data even when power supply is stopped. The semiconductor device includes a first transistor, a second transistor, a third transistor, and a capacitor. One of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor and one electrode of the capacitor. A gate electrode of the second transistor is electrically connected to the other of the source electrode and the drain electrode of the third transistor.

Provided are a thin film transistor substrate and a display using the same. A display includes: a first thin film transistor, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer being disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer, and an etch-stopper layer disposed on the oxide semiconductor layer.

An active matrix organic light emitting diode (OLED) display device includes an array of pixels, each pixel including an OLED, a driving transistor (DT) coupled to drive current through the OLED, a storage capacitor, and a scanning transistor (ST) coupled to control charge on the storage capacitor corresponding to a data voltage for said pixel. The display device also includes a timing controller configured to control the ST of each pixel to update the charge stored on the storage capacitor of each pixel at a frame rate including at least one frequency within a range of 1-10 Hertz (Hz).

The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

The invention allows formation of LTPS TFTs and TAOS TFTs on the same substrate. The invention provides a display device including a substrate having a display area in which pixels are formed. The pixels include a first TFT made of a TAOS. The drain of the first TFT is formed of first LTPS 112. The source of the first TFT is formed of second LTPS 113. The first LTPS 112 is connected to a first electrode 106 via a first through-hole 108 formed in an insulating film 105 covering the first TFT. The second LTPS 113 is connected to a second electrode 107 via a second through-hole 108 formed in the insulating film 105 covering the first TFT.

A semiconductor device with a reduced layout area of transistors is provided. The semiconductor device includes a first transistor including a first oxide semiconductor film and a second transistor including a second oxide semiconductor film over a substrate. When the oxide semiconductor films are subjected to electron diffraction, the ratio of the integrated intensity of luminance of a diffraction spot derived from c-axis alignment to the integrated intensity of luminance of a diffraction spot derived from alignment in any direction in the first oxide semiconductor film is higher than that in the second oxide semiconductor film. In addition, part of the first transistor is located between the second transistor and the substrate.

To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first to third oxide semiconductor films contain the same element. The second oxide semiconductor film includes a region where the crystallinity is lower than the crystallinity of one or both of the first oxide semiconductor film and the third oxide semiconductor film.

The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.

The present disclosure relates to an array substrate and a method for manufacturing the array substrate. The array substrate includes a substrate having a display region and a peripheral region surrounding the display region, the display region including sub-pixels arranged in an array, and a plurality of thin film transistors located on the substrate, including a plurality of first thin film transistors located within the peripheral region and a second thin film transistor located within each sub-pixel of the display region, wherein there is a first distance in a row and/or column direction between first active layers of the first thin film transistors and second active layers of nearest neighbor second thin film transistors, and there is a second distance in a row and/or column direction between adjacent second active layers, wherein the first distance is substantially equal to the second distance.