A display apparatus including a first thin film transistor including a first active layer, and a second thin film transistor disposed on the first thin film transistor and including a second active layer, in which a material of the first active layer is different from a material of the second active layer, and a channel area of the second active layer overlaps a channel area of the first active layer.

This disclosure provides an array substrate, a method for preparing the array substrate, and a display panel. The method includes: forming a first thin film transistor and a second thin film transistor on a base substrate. In the formation of an active layer of the first thin film transistor, by using an eutectic point of the catalyst particle and silicon, and a driving factor that the Gibbs free energy of amorphous silicon is greater than that of crystalline silicon (silicon-based nanowire), and due to absorption of the amorphous silicon by the molten catalyst particle to form a supersaturated silicon eutectoid, the silicon nucleates and grows into a silicon-based nanowire. Moreover, during the growth of the silicon-based nanowire, the amorphous silicon film grows linearly along guide structure under the action of the catalyst particle, thus obtaining a silicon-based nanowire with a high density and high uniformity.

A display panel driving circuit, an array substrate, and a method of fabricating the array substrate are provided. The display panel driving circuit includes a plurality of transistors. The transistors include a low leakage current thin-film transistor including a semiconductor layer. The semiconductor layer includes a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer. A material of the first semiconductor layer or the second semiconductor is low-temperature polysilicon, and a material of the other has a carrier mobility less than a carrier mobility of the low-temperature polysilicon.

Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOT FETs and fully depleted SOI FETs may be provided.

A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.

A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.

A display device includes: a first semiconductor layer on a first buffer layer, and including a first active layer; a first gate insulating layer on the first semiconductor layer, and covering the first active layer; a first conductive layer on the first gate insulating layer, and including a first gate electrode; a second conductive layer on the first conductive layer, and including a first source/drain electrode; a first interlayer insulating layer on the first conductive layer; a second semiconductor layer on the first interlayer insulating layer, and including a second active layer; a second gate insulating layer on the second semiconductor layer, and covering the second active layer; and a third conductive layer on the second gate insulating layer, and including a second gate electrode and a second source/drain electrode. The first gate insulating layer and the second gate insulating layer include different insulating materials from each other.

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.

The present disclosure relates to the field of display technology, and provides a display substrate, its manufacturing method, and a display device. The display substrate includes a display region and a GOA region. An active layer of a TFT at the GOA region at least includes a first oxide semiconductor layer and a second oxide semiconductor layer arranged on the first oxide semiconductor layer, and the first oxide semiconductor layer is arranged between the second oxide semiconductor layer and a base substrate of the display substrate and has a carrier mobility of smaller than the second oxide semiconductor layer.

An array substrate, a method of manufacturing thereof, and a display panel are provided. In the array substrate, a lesser thickness of an active layer in a GOA area achieves improved response time of thin film transistor in the GOA area, and a greater thickness of the active layer in a display area reduces diffusion of photons in the active layer, so as to decrease an influence of negative bias of thin film transistor in the display area. Additionally, different demands for characteristics of the array substrate in the display area and in the GOA area may be met, such that quality of the display panel may be improved.