H01L27/127

GATE DRIVING CIRCUIT AND MANUFACTURING METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY DEVICE

Provided are a gate driving circuit and a manufacturing method therefor, an array substrate, and a display device, relating to the technical field of display. At least one transistor in the gate driving circuit comprises a first light-shielding layer made of an electrically conductive material, and the first light-shielding layer is connected to a first gate metal layer of the transistor, such that two electrically conductive channels are formed, and the ON-state current is increased, thereby effectively suppressing negative drift of a threshold voltage.

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE

The present disclosure relates to the field of display technologies, and in particular to a thin film transistor and a method for manufacturing the same, an array substrate and a display device. An active layer of the thin film transistor includes at least two metal oxide semi-conductor layers, the at least two metal oxide semi-conductor layers include a channel layer and a first protection layer, and metals in the channel layer include tin, and at least one of indium, gallium and zinc. The first protection layer includes praseodymium used to absorb photo-generated electrons from at least one of the channel layer and the first protection layer which is under light irradiation and reduce a photo-generated current caused by the light irradiation.

BURIED LOCAL INTERCONNECT BETWEEN COMPLEMENTARY FIELD-EFFECT TRANSISTOR CELLS
20230089185 · 2023-03-23 ·

An integrated circuit component includes a first layer including first and second areas of epitaxy material. The first layer has a first polarity. The component further includes a second layer including third and fourth areas of epitaxy material. The second layer has a second polarity that is different than the first polarity. The third area is arranged at least partially above the first area, and the fourth area is arranged at least partially above the second area. The integrated circuit component further includes an interconnect in direct contact with one of the first area and the third area and in direct contact with one of the second area and the fourth area. The interconnect has a top surface that does not extend substantially above an uppermost surface of the second layer.

MOTHERBOARD AND MANUFACTURING METHOD FOR MOTHERBOARD

The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

Thin Film Transistor, Semiconductor Substrate and X-Ray Flat Panel Detector

A thin film transistor includes a gate electrode, an active layer, a gate insulating layer located between the gate electrode and the active layer, and a source electrode and a drain electrode electrically connected to the active layer. The active layer includes a channel layer and at least one channel protection layer; a material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. The at least one channel protection layer is a crystallizing layer, and metal elements of the at least one channel protection layer include non-rare earth metal elements including In, Ga, Zn and Sn.

Semiconductor device

A transistor in which shape defects are unlikely to occur is provided. A transistor with favorable electrical characteristics is provided. A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a transistor. The transistor includes a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer. The first insulating layer is positioned over the semiconductor layer. The metal oxide layer is positioned over the first insulating layer. The functional layer is positioned over the metal oxide layer. The conductive layer is positioned over the functional layer. The semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions overlapping with each other. In the channel length direction of the transistor, end portions of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are positioned inward from an end portion of the semiconductor layer. An etching rate of the functional layer with an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid is lower than an etching rate of the conductive layer.

Display device and method of manufacturing the same

A display device may include a substrate, a buffer layer on the substrate, a first active pattern on the buffer layer, the first active pattern having a first thickness, a second active pattern on the buffer layer spaced from the first active pattern and having a second thickness smaller than the first thickness, a first gate insulating layer on the first active pattern and the second active pattern, a first gate electrode on the first gate insulating layer, the first gate electrode overlapping the first active pattern, and a second gate electrode on the first gate insulating layer, the second gate electrode overlapping the second active pattern.

THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE COMPRISING THE SAME
20230081823 · 2023-03-16 · ·

A thin film transistor substrate can include a thin film transistor on a base substrate, and a capacitor connected to the thin film transistor. The thin film transistor can include an active layer on the base substrate, and a gate electrode spaced apart from the active layer to at least partially overlap the active layer. The capacitor can include a first capacitor electrode disposed on a same layer as the active layer of the thin film transistor, and a second capacitor electrode disposed on a same layer as the gate electrode and overlapping with the first capacitor electrode. The first capacitor electrode can include an active material layer made of a same material as the active layer of the thin film transistor, and a metal-containing layer disposed on the active material layer. The metal-containing layer can include a metal different than the active material layer and can absorb hydrogen.

TRANSISTOR DEVICE, MANUFACTURING METHOD THEREOF, DISPLAY SUBSTRATE AND DISPLAY DEVICE
20230131513 · 2023-04-27 ·

The present disclosure provides a transistor device, a manufacturing method thereof, a display substrate and a display device. The transistor device includes a base substrate, as well as a first transistor and a second transistor that are disposed on the base substrate. The first transistor includes a first active layer. The second transistor includes a second gate. The first active layer and the second gate are disposed in the same layer.

GATE-TO-GATE ISOLATION FOR STACKED TRANSISTOR ARCHITECTURE VIA SELECTIVE DIELECTRIC DEPOSITION STRUCTURE

An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.